When I read this, it became clear that Austin doesn't fully understand the problem...
and then reading this, that Brian does.
How about the sudden inrushes of current to charge and discharge Cout? How about the slowed rise time of the signal you're trying to drive. Why not take advantage of the spiffy new package and increase signal speeds?
Total bollocks, unless of course you're thinking of driving another Xilinx FPGA?
Hear, hear!
YES!
Or let all the IOs slew fast and add a switchable series termination. A new ST option.
Anyway, after watching the show, and thinking about the new packages, I'm convinced things are starting to look better. In the future, Cio will have to decrease, I imagine we'll see more Rocket I/O type dedicated pins. Cheers, Syms. p.s. Did I hear right or did Xilinx recommend in the presentation that you use a 100 thou thick 24 layer board for these parts? Hmmm, I wonder how much PCB consultants get paid... ;-)