pc board crosstalk analysis

my knowlege on the subject:

i've taken various E&M courses so i know the theory behind it, and am taking a digital systems class so i've ventured into the experimental side, but its mostly been with transmission lines and not pcb traces with hundreds of nets. what can be done besides ground/power planes and thick/far apart traces?

i only know a bit about bypass caps, heard something about parallel plane pairs(?) and routing topology (something about short nets acting as shields to long parallel nets). can anyone explain those? and tutorials / documentation examples for putting it all together in software (how to use constraints and stuff?)

1) Figure out which traces actually matter the most. If you're doing synchronous digital logic, you can always use any extra time available (e.g., the difference between your clock's period and the setup time requirement of the flip-flop you're feeding) to allow the data lines to settle -- you don't care how nasty they look in that period of time. This idea is what leads to people usually taking the most care routing clocks around their board. 2) Control your edge rates: Crosstalk is directly proprtional to dV/dt (or di/dt). Most contemporary FPGAs have the ability to control this, and most people don't actually need to use the fastest setting (even though this is usually the default in the place & route software). 3) Use differential signalling, if possible (it'll chew up a bit more board space) -- differential signals are largely (not entirely) immune to common mode noise 4) The significant electromagnetic field under a trace is largely contained within a distance (left and right) of roughly three times the vertical distance between the trace and the ground plane (this is known as the "3H" rule of thumb). Hence, for a given horizontal spacing of traces, you'll get less crosstalk if you decrease the thickness of the PCB (i.e., drop the vertical distance between the trace and the ground plane). The traces' characteristic impedances will also drop (due to greater capacitance to the ground plane), which may or may not be a problem for you. 5) If you have traces that are electrically long, terminate them properly. 6) Don't cut up your ground plane!

Pick up a copy of Howard Johnson's "High Speed Digital Design: A Handbook of Black Magic"

or a similar book. Although John Larkin will correctly point out that Howard is sometimes giving you an explanation so simplified as to be a bit laughable in its predictions, if you do just follow Howard's advice the worse thing that happens is that you end up having extra layers on your PCB and greater trace spacing that you really needed. That's undesirable, but nowhere near as bad as ending up with a PCB that simply doesn't work. Think of Howard's book as the "Readers Digest" version of design for signal integrity -- the Big Picture is correct (and quite useful if you haven't done this sort of thing before), even if he glosses over a bunch of details that -- long term -- you'll want to know about.

---Joel

Aha! Another ol' fart ;-)

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

| 1962 | America: Land of the Free, Because of the Brave

Here's how we did it in the carbon copy days :-)

Mafrc Popek

I still love playing with the toys :-) I learned on tubes first, then went to semiconductors :) Drafting compass and smith charts, as well..

Regarding crosss talk; besides the physical geometries, which you normally are imposed upon as external constraint, the impedance making will greatly effect the actual measured crosstalk. Sometimes "best match" for power transfer does not equal best match for lowest cross talk, especially for complex loads, such as transducers, certain active devices, due to non-linear behaviors of load.

Marc

innovative antennas, and EMX advise