Yes. We call in the SparseChevron(tm) and it is superior to IBM's 'signal cross (tm?)' (the "best package in the industry")
Did Dr. Johnson help Xilinx design the V4 packages?
No he did not. It was all of our own hard work (with some outside SI experts called in). 'School of Hard Knocks' often leads to innovation.
HJ may have an opinion on the package design, however. Since his reputation as an SI expert is important to him, his opinion will be impartial, and all his own.
It wasn't that our previous packages were terrible, they just were not as good as they could be. With increased speed, and more IOs, and 10 Gbs MGTs, we just can't use "good enough" anymore. It has to be "best."
That may be true. It is also true that to get the improvements we may have made layout more of a challenge. Which would you like to have? A crummy package and terrible signal integrity and lots of jitter, or a great package, great SI, low jitter? That is just too easy.
The FF668 package
It is called making the signal loops as small as possible, thereby reducing inductance. The pcb routing is done automatically anyway. Is there something esthetically pleasing about patterns? You may see the beauty of the SparseChevron once you recognize its benefits!
We do. We have to design characterization pcbs (12+ layers) for all packages. We also have to design demo pcbs with even greater number of layers. Look at the V4 netowrking and memory platforms: pretty tough stuff. But they work, at speed, with great performance. If you can;t make it work, then having an easy pattern is worthless.
Making the package perform well is only half
Well, see the presentation. We might just surprise you with how a bad package can screw up the SI so that no pcb can improve upon it.
The performance depends on how well you can connect it to a PCB.
Again, that is not all true. A bad package pinout can prevent any pcb from having a good return path for power, ground, and signals.
Compettion would like you to think that there are no bad packages, just bad pcb design. Nice trick if you can get away with it. But SI Experts (like HJ), Cisco, IBM, etc. all know better. The pcb can only make it worse, not better.
Hi Austin, Thanks for your reply! I must say it's good to see Xilinx are taking this issue seriously. As you say, the silicon performance improvments necessitate these package improvements. I totally agree that the package can screw up the whole thing. The tales of woe on CAF from folks trying to design with PQ208s show that! My concern was that the package pinout can make it hard to design a PCB layout which has good SI. Power vias turning ground planes into Swiss cheese and all. Ah well, it's about time I did a board with an extra microvia layer.... Cheers mate, Syms.
One caution about micro-vias: I saw a design where the bridge to connect the top via to the micro via made the plane even worse!
If it looks like swiss cheese, then it probably is about that effective. Micro vias are one tool to improve matters, but they have to be carefully used.
Aust> Hi Austin,
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