Anybody know what the REAL story is?

Last year X announced a cool design win using their parts in a new Gibson guitar line. Neat stuff.

Couple days ago I see that A has a press release saying they stole the business with NIOS + Cyclone.

Today I see X saying S3 is the clear winner and Gibson is using it exclusively.

Anyone know what is really going on?

Just curious. The Gibson product is kinda cool regardless of who's part is in it.


Reply to
Patrick MacGregor
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We are just as puzzled as you.

We also saw Altera's press release with Gibson, yet Gibson awarded us the "supplier of the year award" at CES in Las Vegas just moments ago.....

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Could be they are going to use the "hard-to-copy" program in an attempt to reduce costs, or it could be that a new manager or new consultant has decided that they must "take control" and "make decisions."

All very puzzling.

It would not surprise me to hear in a few months that Gibson has an ASIC for their guitar from LSI, Toshiba, or IBM....


Patrick MacGregor wrote:

Reply to
Austin Lesea

Of course, these two do not have to be mutually exclusive...

Not really. One of the better ways to get improved supply and price is to have both brands ready to deploy, so you can 'wave the opposition under the rep's nose'. It also does no harm, if you really do intend to move to ASIC, and if there are questions about availability of either vendor's devices, this also makes sound sense. Where is the puzzle here ?


Reply to
jim granville


This is true. FPGA business is not usually as tough as the commodity business model you describe, but hey, if you did the design with both vendors, then you can bang them together until the lowest price falls out.

I used to do that all the time when I was in the telecom business. Did not like it, but I did it. Only because the phone companies bang the vendors together until the lowest price falls out.

Aust>> Patrick MacGregor wrote:

Reply to
Austin Lesea

Well, I have a hard time believing Gibson would choose to "exclusively use" Spartan 3 when they can't even get them. I also seriously doubt Gibson has the raw volume necessary to justify an ASIC these days. I also think that the smallest "hard copy" Altera part is still more expensive on a per part basis than their Cyclone parts are in the same volume -- and it's even worse when you add in the NRE that A would charge for making the hard copy part. I've done that math on several projects now, and hard copy always lost out.

Given that, it is certainly in Gibson's interest to have alternate sources of chips for their products. Neither vendor can shut down the production run if they decide to allocate the parts to a "more important" customer, or if a delivery schedule moves out another quarter, or two, or... There isn't anything magic about Cyclone or S3 that would preclude using one over the other.

On the flip-side, supporting two different boards adds a bit more burden corporately to Gibson.

I also trust that both A and X will try to "out PR" the other whenever possible. This one just seemed odd to me given that both companies either implied or outright stated a certain level of exclusivity.



Reply to
Patrick MacGregor

It is not often that a company will put two different designs into production. But they will pursue two designs far enough to let the vendors know that they *have* to compete on price. I also worked for a telecom test company who used this technique. Once you get a price from one of these vendors, they almost never raise the bar. So you can then go to production with the winning design.

The downside is that to do this you have to make your HDL code generic, not using any of the special features of either family of parts. This allows you to reuse the code in the next design without a lot of porting troubles.

Reply to
Ralph Malph

Plan 1 is that you write your code so it runs on several vendors, and then you play them against eachother for a low price.

Plan 2 would be to write your code to take advantage of a the features on a specific vendor (and part) so you get denser/faster results, maybe working in a smaller or slower and hence cheaper part.

Anybody have estimates of how much each approach would save? Or how much manpower each approch takes? The first approach might be better if you have a good purchasing dept that likes playing that type of game - offload some of the work to somebody else.

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Reply to
Hal Murray

The second approach only works if you use your code in a single design. Most designers code for reuse since they often work on multiple projects with similar functions. In our case, they had many products that used the same designs, often with additions. So if the original unit used a chip from X and the next generation used a chip from A, they did not want to have to recode the optimizations. On the other hand, they often did have to code for the given chip when they added features to fielded units and needed to push the capacity.

Reply to
Ralph Malph

Perhaps I can shed a bit of light on the Altera piece of this story. I think our press release states things pretty clearly, but evidently has been misinterpreted a bit.

Altera won a design with Cyclone and NIOS in a module that allows a variety of different instruments to connect into Gibson's innovative MaGIC digital music technology. In doing so, Cyclone replaced a competitive FPGA and a small processor. This is not in the guitar but in the technology that enables Gibson to reach a much broader audience with MaGIC. Hence the headline that we are helping Gibson to Spread MaGIC.

It appears as though since the name of the company is Gibson Guitar, many people automatically assumed the release was about the actual guitar without reading the details.

As for why Gibson chose Altera, as I understand it there were both technical and business reasons behind their decision. The combination of NIOS and Cyclone fit the application well. I also believe that Gibson sees the benefits of a two vendor model.

On the guitar side of things, I don't have any reason to doubt that Gibson intends to use Xilinx in production for the Guitar. While I could speculate further, it would be innappropriate and unprofessional.

Hopefully that sheds some light on what Altera announced. Any confusion on the topic was purely unintentional.

Tim Colleran Altera Corporation

Ralph Malph wrote:

Reply to
tim colleran

The architectures for A and X are so close in the latest devices that there are few device primitives that cannot be inferred by synthesis using generic code. So I would use Plan 1 for new designs just for code clarity and ease of simulation. The only reason I might even consider using Plan 2 might be to reuse working code.

In a large company, engineers might best leave final price negotiations to purchasing. In a small company, it is more important to establish a good relationship with an fpga distributor than it is to play price games. The distributor is in the best position to get you proto samples of that new part that isn't quite available yet.

-- Mike Treseler

Reply to
Mike Treseler

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Hi all,

I have worked 2 years for GIBSON in Sunnyvale as a Senior ASIC engineer in the MaGIC design team together with Jeffrey Vallier... I could answer a lot of questions asked here into detail, but I'm bond to confidentiality... I'm still 'theoretically' a GIBSON employee, but in a 'transition state' after

3 months of unpaid-leave-of-absence...

Without sacrificing confidentiality I can say:

- that the original plan was to have a GIBSON ASIC as the final solution...

- I and Jeff favoritized Xilinx because of various reasons as a platform

- I mentioned multiple times to management that using FPGAs would be the best solution when it comes to required flexiblity and the number of chips required per year ( to get a real total cost advantage of an ASIC solution compared to an FPGA solution you have to use an advanced process line together with a 100.000 chips/year.... vendors of this process lines require a multi-million dollar revenue in order to run your design, neglecting some additional NRE costs that are required...)

- there will be definately no GIBSON ASIC soultion in the next months.... (based on the design status and normal ASIC vendor lead times and requirements)

- for most of the time there were 2 people working on the design (Jeffrey and me)

- in the last year there was an additional 3rd person working partially on the design (he was revising/changing the MaGIC spec continiously...)

- Jeffrey left GIBSON and joined a company in Korea 3 months ago...

- the original code was highly portable, scalable and parametrizable using an OOHD design technique that was synthesizable easy and fast with FPGA Express or Synplify (incorporation of RAMs and the usage special architecture features could be changed easily before resynthesis for a new platform without sacrifying architecture optimization [the instantiation of RAMs is different for each ASIC and FPGA vendor])

- the team worked the whole time with budget and tool restrictions...

Hopefully I was able to add some more detailed parts to the puzzle to make it easier to see the whole picture... Happy puzzling...

cul8r, AS (Andreas Schmidt) aka 'The Wild German Guy'

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Patrick MacGregor wrote:

Reply to
Dipl.-Ing. Andreas Schmidt

I don't really care about this particular product (I'm old school and my Les Paul goes into a '62 Fender Bandmaster), but I wanna know the REAL story as to why Les Pauls, even the expensive ones, require a fret dress right out of the box.


Reply to
Andy Peters

Hi Tim.....;-)

Brian Dipert Technical Editor: Mass Storage, Memory, Multimedia, PC Core Logic and Peripherals, and Programmable Logic EDN Magazine:

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Reply to
Brian Dipert

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