Shift register power on.

That's pretty bad. MR should clear everything. And OE floats the outputs, which may make trouble for you.

We use a lot of TPIC6595s as relay drivers, and it has the same silly architecture. We disable the outputs (with the /G pin) until after the first full shift/latch cycle. But then we don't need to use SRCLR, the half-ass reset.

This works. The tricky part was distributing the serial clock to 34 big relay driver chips wired as one giant shift register.

You could save one port pin and one wire by holding OE false after powerup, until the strobe. That would need a little local circuit on each board.

Fortunately, it won't matter in my particular application.

It's difficult to fathom the motivation. It lets one clock in data faster when it has high order zeros, but who would even bother? Perhaps there's another way it could be useful, but I can't see it.

Sylvia.

use something like a 'HC74 d-flop. /clr to your board/uC /por. /pre and /oe to /q and /mr to q high on the D input. clock it and stcp once. You might need to pull up /pre to make sure it's stable. You may need to use the other half of the '74 to give you a 1 clock latency on the stcp and /mr transition.

MSI was never intended to be a one chip solution to many problems. Why not use a more suitable part? There are any number of I2C and SPI driver chips that are much better parts than an 8 bit '595.

MC33996, TLC5922, MAX6966 and many others.

Pull-up (or pull-downs) on the Tristate outputs.

Cheers

If I understand your description correctly, then a 74HC164 is much better suited for the job than the HC595. The HC595 only does you anything good, when you have to catch a byte transition on the parallel input *while* you are transmitting, i.e. shifting the SR.

Klaus

The '164 shows the contents of the shift register as they change, which wouldn't be good if (for instance) you wanted to hold Q0 at 0 while toggling Q3.

The '595 holds the output constant until you tell it, at which time it switches.

Shouldn't be.

Small, low-power CPLD? Yes, the task is vast overkill for such a beast, but it'll work.

If this is an issue, then the HC594 as suggested by Fred before seems to be the solution to Sylvia's problem.

I've used a SIP resistor array driven from an output to "force" multiple pins high and low, programmatically (e.g., to detect if the signals that *should* be sourced on those pins are, in fact, present as well as force them to specific states when "disabled")

That's the part she's having problems with, and if you look at the data sheet it certainly indicates that the reset only goes to the shift register and not the shift-capture register.

Maybe not; can you put in a latch, set HIGH by MR, and only set LOW to enable the outputs by the first or second STCP , with the latch output driving \OE? Or even a retriggerable one-shot, to make a 'slave reset' signal that lasts a short time after the master reset (yeah, I know, it's ugly to include timed logic).

There's probably lots of uses for multiple non-master resets, but i doubt you'd want to commit to an I2C addressable latch for just one little 'not-yet' signal.

Not really. She is using the 595 which has tristate output control which she doesn't want and the 594 has an output register reset which could be connected to the same pin as the shift register reset which would do exactly what she wants.

I can't remember the last time I used a 7400 type device other than a bus buffer and that was actually a level shifter chip.

Whoops -- missed that. I just read up to the HC59 and phased out. Thanks.

Actually, an I2C latch reduces my component count considerably. Some of the outputs from my 5 cascaded shift registers were to drive a diode matrix to let me sample multiple inputs. I can substitute 3 I2C latches, and read the inputs directly.

Sylvia.