Cyclone configuration device

"Martin Schoeberl" schrieb im Newsbeitrag news:i7JNd.33865$ snipped-for-privacy@news.chello.at...

for the serial

EPCS are custom labeled ST serial flash devices 25Pxx

AT25F might be useable as well, but compare the prices, hmm

hm the P1024 was CASON8 (6x8mm), the F1024 is SAP even smaller 6x5mm well if you are sure you want to deal with Atmel and can by the parts and

I am looking for 4MByte serial flash and there doesnt seem to be any alternative to 25P32 and that is unfortunatly only available in SOIC-16 WIDE, so no 4MByte device in Chip Scale available for direct purchases at the moment. Or at least I have not found.

The difference betweeen 1MByte and 4MByte is very important for me, in

NexFlash has pin compatible parts to ST so there is second vendor availables, so I think I stick to 25P32

NIOS?

hm whats the problem?

Antti

the serial

Just use it as normal SPI periphal and use the cyclone_asmiblock for it...

rick

Don't know if it's a problem. Just havn't done it till now and didn't find any documentation about it from Altera.

"Martin Schoeberl" schrieb im Newsbeitrag news:VELNd.33972$ snipped-for-privacy@news.chello.at...

any documentation

Menu: File->Convert Programming File select .JIC select your serial device select your fpga add .sof convert start programmer add .JIC program

That should be it! when it works :)

Antti

Antti,

you misunderstood me. I was asking about programming it FROM the FPGA. You know this ASMI stuff.

Martin

"Martin Schoeberl" schrieb im Newsbeitrag news:I3MNd.33985$ snipped-for-privacy@news.chello.at...

using

know this

sorry I am bit off today catched some cold, hope it doesnt cathc over newsgroups..

I bet you get no replies regarding the ASMI stuff. I looked into a little a long time but havent actually done anything - from simple reason I still dont have any of your nice cyclone boards on my desk :) The acex board I have, I would like to give it away..

It should be possible but you might have to dig into library sources, etc. etc..

Antti

Antti,

This wouldn't help, as these boards are configured with parallel Flash and a PLD. I'm just thinking about a new board for JOP and how to minimize part count. I have to beat the S3 Starter Kit in the price...

If you want to solve this issue with a Cyclone I can give you one board. However, you have to modify it - attache the serial Flash to the FPGA pins in 'some' way and change MSEL0 to 0 for AS.

Martin

---------------------------------------------- JOP - a Java Processor core for FPGAs:

Rick,

Have you allready done it? A small code snippet would be nice.

Martin

---------------------------------------------- JOP - a Java Processor core for FPGAs:

enjoy (o; rick

Well.../OE should be obvious to all (o;

This is documented in the EPCS datasheet...not the RPD file but the bitorder the FPGA reads in.

rick

The only thing you have to worry about here is /OE, it's an active low output enable for the FPGA to drive the interface.

Also note that when you're programming the EPCSX/replacement you have to bit reverse the bits of each byte from the RPD file (I think it's called from memory).

I have had this working by hand (ie manually driving my interface design) but haven't got software to drive it properly yet. I'll hopefully get some time to look at this soon and will release any results.

I don't know why Altera didn't document this feature, it's a real selling point and I hope CycloneII includes the same core.

Hope this helps,

Nial

------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design