Q) fast serial communication method

Jun 28, 2004 8 Replies

Hi, Dears.



These days, I am searching the fast serial communication method.



It has some conditions.



a. fast(more than 10Mbps) -- (No, Ehernet), (No, CAN bus) b. use the differential line c. (If possible) one chip solution like UART...



I will use it board(PCB) to board(PCB) data exchange.



Please, help me.



Thank you.



Suhyeong Jang. snipped-for-privacy@daum.net


The AMD TAXI chips might still be available. That was very fast.

Leon

--

Leon Heller, G1HSM http://www.geocities.com/leon_heller

PCI-Express?

Grant Edwards grante Yow! I'd like MY data-base at JULIENNED and stir-fried! visi.com

How fast do you need to go?

100Base-T Ethernet using an SMSC LAN91C111 nearly fulfils these requirements - it needs a transformer but is basically a one-chip solution.

Firewire? USB2?

Cheers TW

Upto several Gb/s?

Differential transmission and reception

Hmm

How about LVDS (embeds clock in the data stream), simple chips available meant for backplane interconnect, or possibly PLDs (Altera etc) which have LVDS pins.

Look at National Semi for LVDS, Texas do a TMDS similar thing, Altera etc. for PLDs.

Just a few thoughts.

Main place I have used them for LCD interconnects, but considered them for other applications.

Paul Carpenter | paul@pcserv.demon.co.uk Main Site GNU H8 & mailing list info. For those web sites you hate.

On Mon, 28 Jun 2004 12:16:22 +0100, "Leon Heller" wrote in comp.arch.embedded:

AMD discontinued their TAXI chips quite a while ago, as I recall. Cypress had some sort of equivalent that we used for a redesign.

Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://www.eskimo.com/~scs/C-faq/top.html comp.lang.c++ http://www.parashift.com/c++-faq-lite/alt.comp.lang.learn.c-c++ http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.html

There are the "serdes" solutions, i think offered by TexasInstruments and there are a bunch of parallel LVDS lines driven by some FPGA. The "serdes" is basically parallel to seriell and the other way round with GBit speeds on the serial. I'm only halfway familiar with the Altera FPGA families, which offer from 400Mbit to 3GBit per LVDS channel.

Rene

Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net

You need to give some more information on :

- how much faster than 10Mbps ?

- Distances and noise immunity expected ?

- is isolation a requirement ?

- What devices/information is being linked ?

SPI Bus variants can go > 10Mbps, and a ring topology addresses by position, so can be fast and simple from a single master. For more complex system link busses, there are quite a few BUS schemes, going up to past 1GBps.

-jg

Hi J,

You have the Synchronous Serial Interface (SSI) architecture that can help; but I am not sure that current circuit with SSI interface with a differential line is available.

JaI

J wrote:

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