Serial communication IO reduction

I have 20 identical IC's to drive using serial communication most likely with an FPGA or pic. The comm IO's are serial in, clock, and latch. There are other lines but I can combine them into one. Also each IC has a serial out for cascading. The IC's simply contain a shift register that is latched for functionality when the latch is enabled.

Because of speed issues I need to parallel the communications to run at a decently low clock. If a chip is not cascaded then it requires a clock from 500kHz to 1Mhz depending on how fast I want to run it. Multiply this by the cascade size.I have designed the system by cascading 5 IC's which leaves me 4 groups and requires a clock of

2.5Mhz to 5Mhz. This is pushing the limits of my system design as the IC's are spread out over a large distance.

In any case the question is about combining the serial lines. I believe I can combine the latch and serial in lines and only have distinct clock lines for each IC. This way I can parallel all the IC's using an fpga and possibly a pic.

That is, there would be 20 serial in lines, 1 common latch, and 1 common clock. In this way I would simply cycle in the data that is already latched to keep the data in the IC unchanged. This requires updating constantly which consumes power and increases noise among other things.

Alternatively I could have 20 serial in lines and 20 latches or 20 clocks and 20 latches or 20 serials and 20 clocks. This requires 41 lines rather than 22. Of course I could go with 20, 20, 20 which would require 60 IO's.

I can cascade in small groups to reduce the IO's even further. I'll have to work on a happy medium.

The question I am proposing has to do with having a common clock and common latch. Is this a bad idea? Note that 1 serial line with 20 latches or 20 clocks do not allow paralleling data and requires increasing the clock rate. The IC's have a max clock rate of 15Mhz hence some need for paralleling. Unfortunately I'm running out of space the pcb and too much paralleling is going to be a routing nightmare.

Also, The IC's are arrange in a 4x5 matrix and ultimately I want to communicate with a central controller that dispatches data to the appropriate IC rather than sending bulk data to all the IC's from an offboard controller since most of the time only a few IC's will need to be updated and I would like a single 1-wire or 2-wire comm with the board.

Reply to
Joo Blow
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Did you ever look into LVDS chips? There are many cheap solutions that take parallel in, serial out. On the other end you place a serial in parallel out LVDS receiver. You can have an FPGA output the LVDS signals directly if you want.

It is a very old idea. It should work up to reasonably high freqeuncies if you route the clock along with the serial path to avoid mismatches in the delay.

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Reply to
Nico Coesel

Sounds like you are trying to reinvent the old RS-485 system.

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