Sensitive List Question

Firstly its called a sensitivity list :) and secondly its really only used by simulators the synthesis tools don't actualy take any notice of what is and what isnt on the sensitivity list when synthesising logic.

I should add that if you have simulated something with an item missing from the sensitivity list,then the reason you get a warning from the synthesis tool is that the behaviour of the synthesised logic may differ from what you simulated because sensitivity list items do have a profound effect on how your simulation will behave.

"Jezwold" schrieb im Newsbeitrag news: snipped-for-privacy@c13g2000cwb.googlegroups.com...

in the end I should just add all my values to the sensitivity list, so that the synthese tool is happy?

yes if you use modelsim you will find an option called synthesis check , or something like that which basically checks that all the items in a process that effect the logic flow have entries in the sensitivity list.

Consider using synchronous processes.

-- Mike Treseler

The reason being I belive that then you can just have the clock in the sensitivity list (and reset if asynch reset).

As long as all logic statements are wrapped in a "if (clk'event and clk=1)" then simulation and synthesis results (in terms of logic) should be the same and any "missing signals from sensitivity list" warnings can be safely ignored (as far as I am aware...)

Cheers,

Ken