If you INSIST on not using a single 300MHz clock, then you could handle the clock domain transfer between CLKI and CLKI_DIV without a fifo using CLKI_DIV as the clock enable for data being transferred to CLKI:
DOMAIN_XFER: process (CLKI) begin if (CLKI'event and CLKI= '1') then
if (CLKI_DIV) = '1') then data_clki
No, you have to use a DCM type solution.
Razzy, How, pray tell, does that help? Thanks, Symon.
I've joined this thread a bit late. Although for this design I agree that a single clock domain at 300MHz and an enable signal is a very clean solution, has anyone considered using a PMCD? This would provide low skew versions of the 300 MHz and
150 MHz that the Xilinx tools should analyze properly and provide a robust solution.John Providenza
Hi John, The OP's assertion that "I can not use DCM" led me to believe that this solution was not to his liking. Cheers, Syms.
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