Sometimes it would be handy to use MCU timer outputs as clock sources. However I haven't seen any information regarding the phase noise of the MCU generated clocks. Assuming the input clock signal is ideal, what level of the phase noise can we expect from an MCU timer generated signals? Would the result be different for the MCUs with or without the internal PLL? Could we assume that the phase noise equals to the internal noise divided by the slew rate? Then what is the ballpark of the internal noise?
I guess the same considerations apply to the FPGA generated clocks as well.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
We've gotten well below 50 ps RMS jitter out of Spartans doing lots of clocked and combinational stuff to signals. But it wasn't obvious or easy.
A Spartan3 internally clock-doubling a 40 MHz clock produces an 80 MHz lopsided (bimodal) square wave that has, in effect, about 40 ps RMS of deterministic jitter.
Ordinary HC-type gates can propagate periodic signals with ballpark 10 ps RMS jitter, so effective noise must be ballpark a few millivolts RMS. The worst thing is prop delay vs temperature, which creates delay "wander." A uP may add a bunch of ground bounce noise as it crunches instructions.
You can always clean up a timer's output by resynchronizing with an external d-flop.
I'd expect any high-ratio clock multiplier PLL to create a lot of jitter, FPGA or uP.
What sort of numbers do you need? Things like 100 ps RMS should be easy as long as a PLL isn't multiplying much.
Disclaimer: I've never measured the phase noise of an MCU output.
I have however built satcom PLLs using STTL logic parts, for which many of the same issues apply.
Power supply variations cause changes in the propagation delays and the rise and fall times, which translate into phase noise. There's usually crosstalk as well, so the phase noise will depend on what else the chip is doing when the timer fires. So whatever answer you get will depend on external circumstances.
Disclaimer: I've never measured the phase noise of an MCU output.
I have however built satcom PLLs using STTL logic parts, for which many of the same issues apply.
Power supply variations cause changes in the propagation delays and the rise and fall times, which translate into phase noise. There's usually crosstalk as well, so the phase noise will depend on what else the chip is doing when the timer fires. So whatever answer you get will depend on external circumstances.
elm-chan has investigated this. Have a look at his page, even though it is in Japanese, the pictures are interesting. His other stuff is very good too, much of it in English.
Ok, you've got the HW pointers already now. Be careful with the source itself. Often uCs use what marketeers call digital frequency loop or similar. In order to generate the more odd ratios they skip a cycle once in a while. That can make for nasty surprises when this comes out of the timer. So employing the typical watch crystal -> high frequency method may not work for you.
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The noise inside the chip of the SiLabs F120 appears to be about 2.5V/
2000. I base this on the performance of their internal 12 bit ADC. I's bet that the actual number varies all over the place from location to location inside the chip.
Do you consider systematic variations to be part of the "jitter" of the PLL. If you run the F120 on a 22MHz crystal than then multiply up to 88MHz in the PLL, I'd bet there would be a fairly obvious 4 cycle long pattern in the noise of the 88MHz
l.
In the FPGA case, you can make sure that the output is synced up to the clock before going to a pin. In some MCU designs, the counter signal will go through a lot of logic on the way to the actual pin. At each stage more noise gets added in.
On the BlackFin DSP, the jitter of the timer generated signals appears to be about 150...200ps rms (measured). This is without any activity on the bus or I/O; the power supplies and the layout are OK. The jitter is clearly correlated with the internal activities of the DSP.
BTW, I recall the old book on the synthesizers where they claimed that the ordinary 74xx gates are quite low noise: something like
-140...150dbc. The schmidt gates are noisier then the simple gates. But the main rule is never run unrelated frequencies through one logic IC: there will be the intermodulation products with the levels -40...-60dB all the way.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
When you use divider chipss, the LSB has low timing jitter but all of the higher ones are modulated by the lower bits.
74HCxx chips can be very low noise if you keep the supplies quiet. Grouping together chips that contain signals that won't mess with each other and then providing local regulation of the supplies of the groups worked very well to keep the noise low. The surface mount little regulators don't need heat sinking so it doesn't add much to the size of the PCB.
We're using some crystal oscillators that are available at custom frequencies on short notice. I think they're digitally programmed, and do tricks like that. Not good for jitter.
The edges of alternate cycles of our 80 MHz clock seem to be displaced in time, but don't "jump around". The clock is internally doubled from
40 MHz. It's similar to the wobble you'd see with a classic tuned-circuit frequency doubler. I suspect they are using taps on a delay line to do the doubling.
Yup, everything talks to everything on-chip. The clock nets seem stiffer than long signal routing paths. Maybe.
I assume you mean: FZT2222 or equi. --+----------- ----------- ! \\ /e ! ----- ! ! ---/\\/\\------+ ! --- --- ! GND
The down side is that the voltage out depends on temperature.
The good old LM7805 type regulators can be had in surface mount. If you give them about 3V of head room they have good power supply rejection.
In both the LM7805 and the 2n2222 like cases, I have found that an impedance in the incoming power line still helps. An RF bead will eat any RF that is trying to come down the path. Harmonics of your other switching signals can be trouble makers.
BTW: You will notice if you search what I said carefully that the term LDO doesn't appear. I find them to be dreadful also. The fact that they require that their load appear slightly resistive over a band of frequencies is sloppy design in my opinion.
Yes, but so does the chip timing itself because that'll heat up, too. In most of my designs things are paired, quad'ed or otherwise matched up anyhow. Other times it's servoed. This takes temperature out of the equation. But none of those tricks can get rid of phase noise once it's in there. So the supplies have to be squeaky clean.
And very nice de-icing behavior :-)
Yes. Or a small resistor.
That's what the above is for ;-)
Unless you roll your own. Seen too much grief with LDO chips. Way too much, all the way up to uncovering non-documented behavior. When you hear a team of engineers at a major semiconductor mfg shuffle tons of paper at the other end of the phone line and then one of them exclaims "Oh dang!" then the end of the rope is near.
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In one example designed by someone I work with, the timing wasn't servoed but it was measured as part of a continuous self calibration. The product was mostly a period measurement. Every second pulse through the important path was a calibration one. The circuit turned a fraction of a clock cycle into an analog voltage that went to an ADC. The calibration pulses checked the two ends of the span of the ADC so that it could be kept as 4096 meant a full cycle.
The current isn't usually all that much in the parts where the phase noise really matters. The display and the RS-232 and the network and all that other stuff can be run on a switcher that uses hit and miss regulation with a chattering relay.
t
Yes but that doesn't look nearly as scientific. Part of the job is to keep the masses mystified :>
.
A double yes.
t
In the roll your own, you are free to not make it need a resistive load and I assume this is what you do. You can also fly the control circuit at the same AC voltage as the power input to do a feed forwards.
If the control circuit doesn't make a lag over about 45 degrees, the load can be a pure capacitance without trouble. I usually would put a small resistor in series with the emitter or source of the pass device. This way, the gm of that section is better known.
I had a phone call like that with someone at Linear a while back on a switcher chip. The LT1246 switcher has a bug. If you pull the Vc pin all the way to ground, the output can do random stuff. It adds a diode to the design to prevent this. Kludging the diode in on the prototype fixed the problem. The guy at Linear assured me that they would fix the datasheet. I haven't checked that they did.
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