I have quoted (at the end) an extract from the xilinx 5.2.03i trce command which shows the worst path in my design.
The path is a carry chain within an adder but mid-way through the chain, it jumps to another column (X45 to X39) leading to a big delay!
The VHDL was synthesised using Synplify Pro.
Sometimes, for other filters with the same style of VHDL, the tools don't do this and maintain the carry chain in the same column which is clearly faster.
Is it Synplify optimisations that are causing this or perhaps the ISE map/par stages and is there any way to avoid it?
Thanks in advance for your time,
SLICE_X45Y5.CIN net (fanout=1) 0.000 AdderChain.tap27_sub_v648_1_cry_8/O SLICE_X45Y5.COUT Tbyp 0.092 tap27_sub_v648_1_s_9_n
SLICE_X45Y6.CIN net (fanout=1) 0.000 AdderChain.tap27_sub_v648_1_cry_10/O SLICE_X45Y6.X Tcinx 1.107 tap27_sub_v648_1_s_11_n
SLICE_X39Y18.F3 net (fanout=1) 0.910 tap27_sub_v648_1_s_11_n SLICE_X39Y18.COUT Topcyf 0.668 tap27_sub_v648(11)
SLICE_X39Y19.CIN net (fanout=1) 0.000 AdderChain.tap27_sub_v648_1_cry_12_0/O SLICE_X39Y19.COUT Tbyp 0.092 tap27_sub_v648(13)