Design analyse methods

So, you have an FPGA on a board and you want to know the value of signals within that FPGA, but you don't want to use any external pins? Hmmm.

Two sensible choices - SignalTap - Not used it, but at a guess it uses internal RAM to store signals, then communicate them via JTAG back to the host PC. VITAL, or Gate Level simulation. OK, its simulation, but (in theory) it is the Place and Route tool's view of what it has just placed and routed, complete with ps accurate delays. You should do a gate level sim anyway, just in case your design has been broken by one of the tools along the way.

-- Ian Poole, Consultant

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Altera provides the SignalTap II tool to allow monitoring live signals inside the FPGA. This solution uses the internal RAM. Details of how this tool can be used are provided in

Hope this helps.

- Subroto Datta Altera Corp.

As Subroto suggests, SignalTap II best matches what you're asking for, in that it does not require debug pins.

Something else that may be of interest is SignalProbe. It lets you bring signals to unused output pins for debugging, without changing the placement & routing (and hence timing) of the rest of your design. So it does require debug pins, but it avoids the chaning timing issues you're worried about.

Vaughn

Best first, second and third step.

Inside the FPGA, don't use vendor core generators. Write your own code that infers what you need.

For memory and other external parts, choose devices with free models or write some code. You may not need a very fancy external model to verify your own synth code.

Once you're done, you can "probe" wherever you like with sim waveforms, and have the freedom to make changes fearlessly.

-- Mike Treseler

Especially given the possibility of testing using post-place-and-route simulation models with back-annotated signals, which include most of the timing issues that can crop up...

I'm not sure I've correctly understood this question, but it seems to me that if you can't test a module in simulation, where you have access to _all_ the internal signals, you'll have an even harder time doing so when you only have access to a limited subset... Could you elaborate? What couldn't be reproduced?

Mike, I'd be interested in hearing why you think this, I'm not sure that I agree.

Pierre-Olivier

This is a trade-off of device utilization verses independence and ease of simulation.

There will always be things you can't infer from code. I'm happy to leave those things unwired.

-- Mike Treseler

Hi,

As in SignalTab from Altera, is there any way of doing similar in XILINX FPGAs?

Regards, Muthu