has any one some hints or tips how to get an Virtex4 LX25-ES configured from SystemACE? we can configure from iMpact and if we load the uclinux kernel from XMD it works too. but now when I try to load the uclinux image from CompactFlash then there are problems if the FPGA is configured by impact then there will always be random sector read errors when attempting to load the image.bin from CompactFlash. On ML300 I had to load from CF in order to access the CF, but with V4LX the FPGA config from CompactFlash doesnt seem to work, the status led blinks once and then the error led goes on. I assume it is the TDO tristate problem with -ES samples, but...
ML401 has systemACE as well and that works! So whats the trick ??
I get this symptom with a V2Pro board. When I load the compact flash with the bit, bmm, and elf file. When I just load the bit file into the compact flash, I get same symptom you get. Also, the error reg in the sysace has a value of 0x000000C0 after the error LED goes on. This doesn't solve your problem, but is another point of data.
"newman5382" schrieb im Newsbeitrag news:1t4Od.15793$ snipped-for-privacy@tornado.tampabay.rr.com...
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compact how? you mean when the bit file in the ACE file containts both fgpga bitstream and elf data? there is now way to directly load the Cf with elf and bmm, or
well with V2Pro boards I havent had problems, except that I wasnt able to access the OPB_sysace unless the bitstream was loaded from CF as well, but this was maybe becuase I did not chanhe the systemace init mode to disable the auto load
I generate the ace file via impact - Prepare Configuration Files - System ACE File - System ACE CF Novice - 128 Mbits Reserve Space - etc - add file download.bit, system.bmm, executable.elf
I read somewhere that the sysace is like some type of JTAG player, I assumed that the elf would get loaded somehow like it does with xmd, except without xmd. Perhaps I am wrong, and that is why it does not work for me. Also, when I try to read a sector via the MPU interface, it goes busy and never goes ready again (i.e. Status Reg bit 8 goes low and stays low even after I read out a sector of data.) The sector reads 256 16 bit words of the same value. When I use XSysAce_IdentifyCF, I get the expected Signature, but all the other fields come back with the Signature value also, and bit 8 of the status reg never goes busy.
"newman5382" schrieb im Newsbeitrag news:655Od.15899$ snipped-for-privacy@tornado.tampabay.rr.com...
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ahok yes that proper, it is adds the bit+elf as ACE same as you can create a BIT with FPGAbit+elf
except
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correct: systemace is a PicoBlaze based sort of SVF player if you look at the ChipScope manual then you see partial listing of the PicoBlaze code as example how to use ChipScope load mnenmonics :)
so the .ELF file (if that is for PowerPC ) will be converted to SVF that uses the PowerPC JTAG and it is "played" after the FPGA bitstream is loaded so yes it kind similar of how it is done by XMD
to bad the .ACE format is closed information if there is trouble then all Xilinx users are STUCK. doesnt work and end of story.
hm in your case I still wonder what the problem is
you have v2pro and PPC based design with OPB Sysace right? try this, create a small sysace test - if I find sources of my system ace image loader you can use that, or maybe you have a copy it was downloadable before I had to refromat openchip webserver
so compile the program into BRAMs! in XPS update bitstream or do it with impact so you will have download.bit that contains the fpga and ppc code, then IMPORTANT create ACE from this bitstream do not add any elf to the ACE !!! the program code is .BIT ! copy to CF card, and configure from the CF
now the systemace SHOULD really work.
if you still have trouble then open a gazilion of webaces :)
There is a utility SVF2ACE available from xilinx. One can use this to create an .ACE file most .SVF files. IMPACT can be used to generate an SVF. We have found it useful when debugging configuration issues to remove the bitstream and/or various other JTAG commands, from the SVF and test with a minimal ACE file to verify that that the JTAG chain is in intact, and will run at speed.
We used this technique in various stages of a V2Pro design to discover first that we needed a pullup on TDO, and z few months later, that internal to our bitstream we had set up the PPC405 cores on the JTAG chain incorrectly, and at startup this problem was hosing JTAG.
Regards, Erik.
--
Erik Widding
President
Birger Engineering, Inc.
(mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233
(fax) 617.695.9234
(web) http://www.birger.com
We had similar problems in trying to load an ACE file from CF--but Only if the ACE file was NOT in the root directory. Turns out the issue is that a Windows 2000/XP formatted CF will NOT work. You must use mkdosfs.exe to format the CF. After that, pretty much it started acting as expected. This may or may not be your particular issue.
This information applies to a V2Pro UltraController product and not to a V4.
I make a special test case where I stripped pretty much everything in the deisng except the opb_sysace, and some gpio to toggle some led's and some uart support for stdout.
I got some code to fit entirely within the brams and loaded it into the compact flash without any elf file stuff. When I boot via the CF, the status led goes green with no lit error led. After it returns from the XSysAce_IdentifyCF routine, the Signature field is 848A which appears correct, but the NumCylinders is also 848A.
It looks like the reads of the buffer are not incrementing the FIFO that would cause the IdentifyMemCard command to end. What bothers me is that I appear to be able to read the other registers OK.
I guess I might have to open a web case, wait for EDK6.3i to arrive, buy Chipscope or borrow a scope, or apply a blow torch to the Memec SysAce card:,) Usually Memec has pretty good reference designs, but this one did not have an MPU interface one for the standalone sysace module. Of course their baseline reference had a bunch of deprecated cores I ended up converting to EDK6.2 sp3. Do you think sysace is going away to be replaced by the platform flash stuff? I'm wondering if I should be researching a more valuable target.
"Bo" schrieb im Newsbeitrag news:9u8Od.2834$ snipped-for-privacy@fe40.usenetserver.com...
hm I think W2k FAT16 formatted CF actually works, at least it worked for me, anyway I am having trouble with V4LX25-ES using a CF card that DID work on V2Pro board. The sector read commands get error, sometimes after 1 Ok sector sometimes up to 10 sectors are read OK. The CF has not been reformatted and the file I am reading (uclinux image) has not been overwritten since the time it worked on V2Pro so I dont think the formatting is the issue
but thanks for the hint, I have had also problems with ACE not in root dir, so that issue DOES exist too in some cases
"newman5382" schrieb im Newsbeitrag news:oShOd.51114$ snipped-for-privacy@tornado.tampabay.rr.com...
replaced
Q: What Memec Board are you using? Q: You can use ChipScope Eval version, but well that may or may not help, try bugging memec-xilinx too
A: Hm, my personal view is that SystemACE should be considered not recommended for new designs. The SystemACE MP is already discontinued SystemACE SC is availabe but hey that only a Virtex-V50 bitstream + docu! The SystemACE chip - HUUGE space requirments on PCB, etc.
I have a project pushed onto my project stack: universal configuration controller - support all type of FPGA mixed chains multiply chains different removable media, etc.. the MMC card FPGA configuration IP core was developed to be used in the "universal config controller". It takes only 21 PLD macrocells to boot Xilinx FPGA in Master serial mode from MMC card (approx
I'm using a DS-BD-2VPxLC Revision 1 UltraController V2Pro System Ace Module DS-BD-SAM Rev 1
By the way, the separate interface connector they tell you to buy from another company is inadequate. The loose fit of the pins makes for intermittant contact. I ended up nibbling the ultracontroller connector housing away to make a direct connection with the ACE board.
I tried the ChipScope eval version, and burnt through the eval period. I'm thinking that I should buy one, I'm just waiting for a pressing need to get one, cause that starts the clock ticking on the time license period? It was never clear to me if Chipscope was a timebased license, or whether you got updates for a year to the different ISE versions, or whether you have to purchase a new license for every ISE update.
On another note, I tried changing the IO power straps to 2.5 volts with
2.5 LVCMOS I/O with a similar change to the SysAce board. It appears that I can no longer achieve an MPU lock, perhaps a write problem. I was thinking of simulating the design now that all the code is contained in BRAM, but since I don't have a model of the XCCACE chip, and maybe its some type of interface compatibility level thing, I'm not sure it would be worth it.
Just to achieve closure on this part of the thread, I found that OEN from the FPGA to the SysAce board was specified to the wrong location in the UCF. Arrgh.
"newman5382" schrieb im Newsbeitrag news:68IOd.10408$ snipped-for-privacy@tornado.tampabay.rr.com...
[snip]
UCF.
Ahh! Good for you!
With the V4LX25-ES the SystemACE doesnt seem to work! Be the reason whatever, at most 10 succesfully secotor reads with correct contents there comes an error that lock ups further communication with systemace So you are lucky I am not...
I wonder that no-one from Xilinx has bothered to comment the issue SystemACE is working on ML401 and there is also LX25 on board so if there is an issue then Xilinx DOES know, or if there isnt a issue then I would be thankful if someone could confirm that systemace works ok with V4LX25-ES without using any special tricks.
Thanks Rudi, but the TDO pullup isnt directly the problem, the SystemACE does read a random number (less than 10) sectors correctly with correct contents after that it gets error and stuck - the sector reads use MPU pins and the JTAG is not involved at all. But... I had pretty much always problems with systemace mpu interface in all cases where FPGA was not configured by the systemace, so if I desolder that pullup and let the sysace todo the config maybe that solves the problem - I kind dont like to modify PCB boards that use 0201 sized components so I have not yet worked with the soldering iron on the Memec V4 board
if I read your message correctly you have two seperate problems:
You cannot configure the FPGA using an ACE file.
You cannot access the DOS partition on your CF card to load image.bin
The first problem might be caused by the TDO tristate errata on some LX25 -ES samples. Whether you do or do not see the problem depends on many factors one of them the order of the devices in the JTAG chain.
What devices and in what order are your devices in the JTAG chain? Is the ACE file generated with the correct parameters, i.e. how do you generate your ACE file?
If you look at (intermediary) SVF files you will see that they consist of a data shifted out on TDI and bits shifted in on TDO. The bits shifted in on TDO are then compared against a mask. If the mask and the TDO bits do not match System ACE CF will stop and generate an error. As a quick test you can remove the TDO part from the SVF file and use impact to generate an ACE file. With that you disable the error checking, i.e. you blindly shift the data into the FPGA.
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