Request for 28 BIT ADDER maximum clock rates for Vertex II FPGAs

Aug 11, 2004 1 Replies

Has anyone tested 28 BIT ADDERS in Vertex II for maximum clock rate thru the ripple carry chain? I have an application That requires a maximum clock frequency of 80 MHz.



Thanks, Bill


80 MHz is extremely slow and easily achieved in any FPGA introduced in the last several years. I would expect that 200 MHz is easy in the slowest speed grade of Virtex-II but I haven't bothered to run the numbers.

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