Hi, All, A 32 bit adder takes two 32 bit inputs. The propogation delay can be significant. if one of those two 32 bit inputs is a constant
1, can the add logic be optimized so that the delay for increment (+1) is reduced? The ohter question is that for 32 bit add, can I achieve 100Mhz on the latest FPGAs?Thanks, Jimmy
Well if you are only going to add '1' you only need a counter, not an adder, but I suspect with the fast carry chains in newer FPGA's, adders may be faster than counters
(Assuming you need a synchronous counter - ripple counters can be much faster)
One of the frequency counter experts here can probably tell you how to make a fast synchronous counter.
A 100 MHz adder should be really easy (a 48 bit DDS I've done runs at
110 MHz in a SpartanII and thats 2 (and 1/2?) generations old)Peter Wallace
Increment is usually done by setting the carry in to 1. In the case of a ripple carry adder, it can be done with a chain of half adders, instead of full adders. I think that makes it twice as fast, 32 gate delays instead of 64.
In an FPGA, it doesn't make much difference, assuming you use one with built in carry logic. I believe that the built in carry logic is faster than a carry lookahead adder at 32 bits, maybe not by 64 bits.
-- glen
Is that true on FPGAs?
I'd expect that half and full adders would use the same carry chain, generally dedicated logic. So the speed would be the same.
Even if you build your own adder logic, is gate delays the right unit? I'd expect LUT delays, and most LUTs are big enough to contain a whole adder so that will be the same speed as a half adder. (maybe off by a few ns to get started)
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Hal Murray wrote: (I wrote)
The comment was meant to be the non-FPGA case. It may or may not be true implementing a ripple carry adder not using the carry chain in an FPGA.
The discussion of different adder designs only makes sense if you are not using the dedicated carry logic.
Well, both half and full adders have two outputs, so need two LUT's.
There is a real question of when it is better not to use the carry chain. The delay through the carry chain is O(n). The delay through a carry lookahead adder is O(log n), though in an FPGA the constant is somewhat larger. For some value of n a carry lookahead adder is faster, though it also uses more LUTs.
(If you have unlimited gate width it is O(1), but you never have unlimited gate width without some other cost. I am not so sure it couldn't be done with Altera's cascade chain, but it would take a lot of logic.)
-- glen
Not really. A straight forward 32-bit adder and subtractor both are approcimately the same size and delay in an FPGA. But depending on you application you might be able to do a pipelined adder or carry save adder. (Cut the carry chain in pieces by flip-flops) Or you can count the lower bits by ring counter and use adders only for the higher bits.
IIRC about 500 Mhz in Virtex-4. Even in older low cost FPGAs like Spartan-2 some 32-Bit Processors run close to 100 MHz so getting the adder to work at that frequency should really be no problem.
Kolja Sulimma
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