recovery/removal timing

If your D input is 1 then the timing between reset deassert and clock will determine whether the flop stays 0 or flips to 1.

If your D input is 0 then it shouldn't matter because you are choosing between staying at 0 or loading a 0. Its the same result either way.

The problem is that this depends on how the flop is implemented. If you build a flop using multiplexers and don't use glitchless muxes then it would be possible to see a 1 in this situation.

Your silicon vendors data sheet should spell this out. If it is missing or ambiguous then be afraid, be very afraid.

John Eaton

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jt_eaton
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If you violate timing you should not necessarily expect things to work properly so saying "...choosing between staying at 0 or loading a 0. Its the same result either way" on your second example is rolling the dice and hoping you won't get unlucky.

Kevin Jennings

Reply to
KJ

the

Well in that case how do we explain that the well documented reset sync design works.

I mean that design that connects reset to async port of two stages synchroniser but connects D input of first register to '1'. If it is matter of dice that design would not be reliable as claimed. (also known as filtered reset design)

Zak

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Reply to
zak

Several reasons:

- If it really was so 'reliable' then you would only need one stage synchronizer, not two. But you do need two or more in order to be reliable because you will likely be violating timing on each flip flop in that reset synchronizer.

- The resets you are talking about typically happen once per power up, not millions of times per second so the chances of you seeing it fail are slim

- If you get an *extra* errant reset clock cycle for some reason you wouldn't know it because the system wouldn't reset. It's only if no reset gets generated that you *might* notice that things are not as they should be.

- Most flip flops in a design do not need to be reset with a global reset at all. Those that don't have that need will be unaffected by whether or not there actually is a reset to that flip flop.

Kevin Jennings

Reply to
KJ

reliable

reset

I think you are misunderstanding the filtered reset design. It connects reset to async port of BOTH flops. So it is not worried about second flop i.e. no problem will occur there if reset is released near its clock edge and there is no third flop to put it right.

Moreover Altera says this design metsatbility proof (I assume 100%)

Zak

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Reply to
zak

It has been demonstrated time and time again that there is no such thing as "metastability proof" in FFs.

This also can occur in mechanical devices and I just realized that the penultimate mechanical time piece is subject to this problem. The Shortt double pendulum clock has a mechanism that speeds up the slave pendulum when needed based on the relative timing of the two pendulums. The mechanism that detects this is subject to metastability or a similar effect. When timed just "wrong", on the cusp of decision between fast and slow the mechanism misapplies the speed up mechanism giving a chaotic jolt to the slave pendulum (potentially the opposite of the intended direction). I expect this perturbation has little consequence, but it is interesting that it happens.

The kicker on the master pendulum uses a gravity lever to give it a push every 30 swings. This is timed by the slave pendulum, so there will still be small perturbations in the strength of the push, but nothing like metastability that I can see.

--

Rick
Reply to
rickman

Or perhaps you're misunderstanding it. I'm assuming that you're referring to 'Synchronized Asynchronous Reset' in chapter 12 of the Quartus handbook (specifically, Figure 12-20) [1]...but who knows

They made no such claim in this section. Altera states no reason for havin g the second flip flop, but I would claim that it is there specifically for metastability protection. As with any metastability protection, that seco nd flip flop will not be a 100% guarantee, but it will be close enough to f or practical purposes.

You can assume whatever you want based on your incorrect recall of the circ uit. That would be rolling the dice again.

Kevin Jennings

[1]
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Reply to
KJ

Zak - very good point - you're analysis is spot on. Looking back at my designs, I see I am now using the Xilinx recomended reset synchronizer, same as discussed here. You're right however, in that using that methodology depends on the assertion "If D is same as Q" on the FF, the clock recovery check isn't neccesary. Which I advocated against depending on in my initial response. Looks like I'm not following my own advice.

But I think it's safe for the reasons I stated - Xilinx recommends it, they know the Flop internals, therefore, they understand the internal behaviors of the design.

Looking back, however, I noticed I PREVIOUSLY used a different reset synchronizer:

reg [ STAGES - 1 : 0 ] reset_in_D; always @( posedge clk ) if( clk_en ) reset_in_D

Reply to
Mark Curry

ame

y

Except that the device responds to changes on the inputs, not from the stat e of their outputs. In other words, meeting (or not meeting) a timing requ irement does not depend on the current state of the output, it only depends on the inputs and their timing relationship. If you want to believe that "If D is same as Q" on the FF, the clock recovery check isn't necessary." t hat's up to you, but it's a belief that is not grounded in any sort of real ity.

Belief that if something happens to be in the correct state already so that means that you can violate timing and not change that state is a false hop e. It is not what will be guaranteed to happen, it's just something that y ou hope will happen. Find a datasheet that actually states what you believ e.

Kevin Jennings

Reply to
KJ

timing

believe that

necessary."

false

that

It is not a case of output but that this output flags the inner state of the flop as it a case of latching.

Anyway, one thing sure the design that is proven to work (what I stated above) connects reset to async port of BOTH flips so surely the second flop is not protected and that means to me no problem is expected there.

I Should say metastablity safe rather than proof. Sorry.

The question that arises why need connect reset to second flop at all. It serves a different purpose in that if clock stops and you want to reapply reset...

Zak

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Reply to
zak

I don't personally know that much about the current state of FPGA internals, but in a related conversation in one of these groups I was told today's technology will not produce an oscillation on the output with a D input timing violation. I would think this is the same thing as the reset not meeting setup/hold timing.

Any ideas?

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Rick
Reply to
rickman

This makes no sense, but I won't belabor it

Again, this is your belief that "no problem is expected there" as well as " proven to work" for that matter. In the 'Synchronized Asynchronous Reset' circuit, Altera states the benefit as being that reset "takes effect almost instantaneously, and ensures that no data path for speed is involved, and that the circuit is synchronous for timing analysis and is resistant to noi se". Now take a look at the 'Asynchronous Reset with Follower Registers' s ection which is similar except that the async reset is not connected to any thing but the first flip flop. In that section, they explain the reasoning with metastability and MTBF. You would have to suspend your belief to exp lain why that circuit is "proven to work". In any case, we're way off the beaten path. My only point in this thread w as what I put in the first post which is "If you violate timing you should not necessarily expect things to work properly". You have an unfounded bel ief that "If your D input is 0 then it shouldn't matter because you are cho osing between staying at 0 or loading a 0. Its the same result either way." You have provided no datasheet that backs your claim of correct behavior in spite of a timing violation so I'll leave it at that and move on.

If you're lucky, you'll go through your career and never have this bite you in the rear. If you're not so lucky, well, hopefully the bite is not too painful and you learn the lesson at that time since you're unwilling to lea rn it at this time.

Kevin Jennings

Reply to
KJ

should

are

behavior

In that case the same concept should hold true for setup/hold as well. If so timing violation will occur even though D input has no transition. What would setup or hold mean then?

Zak

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Reply to
zak

This isn't true in general at all - it all depends on the underlying design of the cell. The SDF format was specifically modified to allow this feature - to do a timing check depending on some other state (i.e. internal state of the cell).

I think you're missing my point - we're agreeing more than disagreeing. I don't advocate depending on that hand wavy, but not documented requirement that no clock recovery check is neccesary when D==Q.

However, as Zak points out, the Xilinx recommended reset resynchronization implies that this is true. If it isn't then the recommended reset synchronization has a timing hazard.

It may be similar to another "heard, but not documented" feature of Xilinx technology - that a LUT output will NOT glitch if you only change one input. Another feature that I wouldn't recommended depending on, but is asked from time to time in these and similar forums, and I beleive Xilinx has stated a "hand wavy" ok.

Regards,

Mark

Reply to
Mark Curry

Can't be possible. It is not matter of technology since you need a known state at sampling window rather than changing state. Technology can improve on timing window but this can't be zero time.

Asynchronous based design doesn't care about timing of flops but logic decisions go through varying delay paths... I heard years ago Achronix trying some ultra high speed fpga based on async design but never heard any update.

Zak

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Reply to
zak

I didn't say there couldn't be metastability. I said there would be no oscillation. Similar to balancing a pencil on end, the state resolves monotonically with an arbitrary delay.

I believe they are targeting only very large customers and have been shipping product for some time now, but I don't recall for sure. It should be easy to check out.

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Rick
Reply to
rickman

No oscillation still doesn't mean correct sampling but will help signal settle for next flop. It remains that input must be in a known state for some finite time to be sampled correctly.

Zak

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Reply to
zak

Recovery and Removal does NOT apply to the D input. It only applies to the application of asynchronous signals (preset or set) and the clock. The D input is a don't care for this timing check. Simply put, if your flip/flo p's asynchronous inputs and clocks change at the same time, or without enou gh timing margin, the flop's output will be indeterminate or unstable. As I said, this is a timing check that is often overlooked by designers.

Reply to
psustew

The

without

unstable. As

Any proof?

If you look at the well tried circuit of reset synchronisation, according to your view it should not work. So somebody should be wrong.

The circuit is this:

'1' connects to D1(input of flop1) , Q1 output wired to D2(flop2). Q2 is now the synchronised reset(if deassrted). Both flops clocked by same system clock and their asyc port wired to reset(arrives ant time). This design cannot be explained to work unless D1 & D2 inputs are relevant to definition of recovery/removal as the design must ignore the situation when clock edge of second flop is too close to reset deassertion. It will then fail 50/50

Zak

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Reply to
zak

the

There is no timing to violate. The vendors data sheet will specify a reset_deassert to clock rise setup time that is only valid if the D input has a 1 that has met the D input setup time.If D is a 0 then there is no timing requirement.

John Eaton

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jt_eaton

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