If your D input is 1 then the timing between reset deassert and clock will determine whether the flop stays 0 or flips to 1.
If your D input is 0 then it shouldn't matter because you are choosing between staying at 0 or loading a 0. Its the same result either way.
The problem is that this depends on how the flop is implemented. If you build a flop using multiplexers and don't use glitchless muxes then it would be possible to see a 1 in this situation.
Your silicon vendors data sheet should spell this out. If it is missing or ambiguous then be afraid, be very afraid.
John Eaton
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