Hi, I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I checked the timing report. Everything is ok, and there is no timing violations. But when I run post simulation, the modelsim reports some timing errors for some registers with $recovery(...). I checked the time when these errors occur. They happened to be the time when reset is de-assertion. I tried to change reset period, but this time other register report $recovery/$setup/$hold errors. It is very strange because I have passed P&R, there is no timing violations, why does these errors orrur? Can anybody help me? thanks very much.
- posted
17 years ago