Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be the only one that works on my setup. I have also assigned the input and outputs to pins using the user constraints, but I did not use the ibuf and obuf (it seemed to compile alright though) so maybe that is my problem. Still wondering what is up with Q/ on the flip flops too.
Thanks,
Fred
juice28 wrote:
> > Hi all,
> >
> > I am an extreme newbe to the xilinx CPLD's. I will try to explain what I
> > have and what I am having problems with. If someone can help out that
would
> be great.
> >
> > After trying to download most of the versions of webpack I finally got
> > version 3.8 to work on my windows 98 setup.
>
> What version is that? I have just installed 5.2i. Are you getting the
> software from Xilinx?
>
> > I am using the schematic entry and using a xilinx xc9572 in plcc44. I am
not
> sure if you need to use verlog or what, but I pick one and then use the
> > schematic entry.
>
> Don't need Verilog or any HDL, if you want to do a schematic.
>
> > My questions are when you make a schematic is it mandatory to use ibuf
and
> obuf on your inputs and outputs.
>
> I think so, I do it. I would be surprized if it will compile without
> using IO buffers. (Pardon my lack of knowing if the right term is
> "synthesize", "translate", "fit", or some combination of the above).
>
> I will await hearing what the experts have to say on this one as well.
>
> >Also none of the flip flops have a /Q
> > output. Do you simply use an inverter on the Q output for Q/ ? I have
made
> a couple of schematics and programmed the chip, but they do not function
as
> I would expect.
>
> When that happened to me in the beginning, it was because the software
> was not using my pin assignment constraints. You should have ran a
> module called "assign package pins" or something like that. I am
> currently puzzled by the convoluted approach to this in Xilinx software,
> which I will likely post about in a few minutes.
>
> But basically, you need to have created a .ucf user constraints file,
> through one means or another. There are GUI programs to do it, or you
> can edit text. This file associates net names (signals) in your design
> (schematic) with physical chip pins.
>
> Now on older software, it was my experience that the software would not
> obey my selections unless I also checked a box in the "synthesize"
> propoerties (right click on "synthesize" part of the project navigator),
> which was something like "use user contraints file" in the old software.
>
> Now things are different, and even more confusing overall, but works
> better by default.
>
> You really need to use 5.2, unless it doesn't support the old CPLD you
> are using?
>
>
> > I think that you must have to be a rocket scientist to
> > figure this stuff out :)
>
> Yes, that is correct. Enroll in a rocket scientist course immediately!
>
> ;-)
>
>
>
>
>
> --
> _______________________________________________________________________
> Christopher R. Carlen
> Principal Laser/Optical Technologist
> Sandia National Laboratories CA USA
> snipped-for-privacy@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
>