Re: Reusing CCLK line after configuration for Spartan-II

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Pablo Bleyer Kocik Contact options for registered users 's Avatar (by Gravatar) posted on
August 25, 2003, 10:01 pm
rate this thread
Reply to this post Reply Tag this thread to save it in your account Save Printer-friendly version of this post Print
Quoted text here. Click to load it

 Exactly, this is what I was referring to. Sorry if it was not clear.
I want to share the same CCLK line for another purpose after the FPGA
has been configured. This will be a toggling 5V signal. Will the
(sleeping) CCLK will have any concerns with that?

 Thanks again. Regards.

Other Related Threads
Jim Kearney Contact options for registered users 's Avatar (by Gravatar) posted on
August 25, 2003, 11:34 pm
Permalink
Reply to this post Reply Tag this thread to save it in your account Save Printer-friendly version of this post Print
Re: Reusing CCLK line after configuration for Spartan-II

Quoted text here. Click to load it

Here is some official documentation - look at Answer # 10046 in Xilinx's
Answer Database.  If this applies to Virtex, I believe it should to the
Spartan II as well, since it is a derivative device.



Other Related Threads
Pablo Bleyer Kocik Contact options for registered users 's Avatar (by Gravatar) posted on
August 26, 2003, 5:46 pm
Permalink
Reply to this post Reply Tag this thread to save it in your account Save Printer-friendly version of this post Print
Re: Reusing CCLK line after configuration for Spartan-II
Quoted text here. Click to load it

 Jim, thank you very much. I had missed that answer (only looked up
for Spartan). I think that will do.

 Regards!

Site Timeline