Re: Reusing CCLK line after configuration for Spartan-II

Aug 25, 2003 2 Replies


> > > Hello.


> > > >
> > > > I have a Spartan-II device connected to a small 5V micro which does
> > > > the configuration process. I want to multiplex the same micro's pin
> > > > for CCLK generation during Spartan-II configuration and as a timer
> > > > output to another device after that. The CCLK signal is 5V -- I know
>
> I think what's he's asking is whether the FPGA will care if the CCLK line is
> toggling after configuration - note the phrase "same micro's pin ... output
> to another device after".
>
> AFAIK, This would be no problem - the FPGA ignores CCLK after its DONE goes
> active so that a chained serial configuration mode works.

Exactly, this is what I was referring to. Sorry if it was not clear. I want to share the same CCLK line for another purpose after the FPGA has been configured. This will be a toggling 5V signal. Will the (sleeping) CCLK will have any concerns with that?


Thanks again. Regards.

Here is some official documentation - look at Answer # 10046 in Xilinx's Answer Database. If this applies to Virtex, I believe it should to the Spartan II as well, since it is a derivative device.

Jim, thank you very much. I had missed that answer (only looked up for Spartan). I think that will do.

Regards!

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