Re: Which Adder?

It infers a ripple carry adder using the fast carry chains. The FPGAs have special logic for implementing fast ripple carry (they actually do a

2 bit carry look-ahead > Hi all,
I am using XST (ISE 5.1i sp3) for my logic synthesis. If I write a > piece of VHDL code as in " c
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Ray Andraka
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Hi, As Ray said, it actually implements 2-bit Carry Look Ahead per slice. Definitely, you can implement any other adder which is of interest to you using LUTs. Pls. go to Xilinx Project Navigator => Help => Online Documentation =>XST User Guide => HDL Coding Techniques to find various signed and Unsigned Adder Implementation.

Regards, Sanjay

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