Re: Which Adder?

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It infers a ripple carry adder using the fast carry chains.  The FPGAs
have special logic for implementing fast ripple carry (they actually do a
2 bit carry look-ahead in hardware, but that is invisible to the user).
Other carry schemes are forced to use the much slower general purpose
routing and logic.  In most cases, the adder built using the fast carry
chains is not only the minimum area, it is also the maximum performance.

Nagaraj wrote:

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Re: Which Adder?
As Ray said, it actually implements 2-bit Carry Look Ahead per slice.
Definitely, you can implement any other adder which is of interest to you
using LUTs.
Pls. go to Xilinx Project Navigator => Help => Online Documentation =>XST
User Guide => HDL Coding Techniques to find various signed and Unsigned
Adder Implementation.


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