Hi Magnus,
strange application but anyhow:
I guess, when I look at ieee802.3ae appendix 44a figure 44a-1 the "sync header bits" were prepended every 64 scrambled bits, by the way a great way to synchronize via barrel shifter.
I think if you don´t want that behavior search for a switch in the xilinx manual to switch of sync header generation, or scramble by yourself. (Do you only rely on the balancing character of the scrambler polynom?)
kind regards, thomas
"Magnus Daniels> >
> The 8B/10B (or any other xB/yB) encoding is there so that you transmit
an
> equal number of ones and zeros. This keeps the transceivers from
saturating
> one way or the other.
>
> Almost true. For the 8B/10B encoding it is certainly true, with its
> running disparity you ensure the DC balance i.e. equal balance between
> 0s and 1s. In SDH/SONET you use scrambling with a PRBS to acheive DC
> balance (an approximation) and in the 64B/66B (10GE) you also use
> scrambling, but only for 64 bits while the other two bits (sync) is set
> in a separate encoder/decoder block. It is this block which I want to
> bypass since it creates an obstacle for my application. I can't use the
> sync bits arbitrarilly, they must DC balance on their own (in 10GE they
> are either 01 or 10).
>
> So, I still need to know where these bits show up on my Rocket I/O.
>
> Cheers,
> Magnus - who defeated the SDH/SONET scrambler with a customized ping!