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VHDL model of Xilinx's Rocket I/O MGT

Good evening, everybody,

Now - before I get cracking on creating a VHDL model of Xilinx's Rocket I/O MGT

- has anyone else done this already? And would they be willing to share it out of the goodness of their heart?

Cheers, Tim.

Reply to
Tim
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There are SWIFT models provided by Xilinx.

Reply to
General Schvantzkoph

Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator

- bit of a bugger if you've only got Modelsim XE.

Reply to
Tim

simulator

The performance is also awful. My testbench takes a 10 to 1 performance hit when using the RocketIO SWIFT models (I use them in both NCverilog and ModelSim, it cripples both of them). Would Peter or Austin please explain why Xilinx decided to use SWIFT models instead of a plain Verilog model. The secrets in a SerDes are at the transistor level not at the logic level. A nice fast bus functional Verilog model would have been prefered by all.

Reply to
General Schvantzkoph

Hello! I have a problem with the swift interface and ModelSim.. when I try to load my project the follow error are returned :# Loading D:/CAE_Tools/Modeltech_5.8/win32pe/libsm.dll # ** Error: Failed to find LMC SmartModel libswift entry in project file. # ** Fatal: Foreign module requested halt. I would like to know the cause of this error.. Best regards, alessio

Reply to
alessio quagliariello

GS,

The ip of the 3.125 Gbs transceivers in the Virtex II Pro was developed by Connexant, and does not belong to us. We do not have the luxury of disclosing the verilog, even if we wanted to.

Now, for the other Rocket I/O (tm) developed by us, we do have that option. I will let the folks in charge know.

Thanks,

Aust> >

simulator

Reply to
Austin Lesea

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