electrical interface problem

You need about a 10dB pad. A suitable method, about 50 ohm in and out (view with fixed font)

High drive output

R1 Low drive input Out + --------- /\\/\\/\\/\\ --------- In+ / / R2 \\ \\ R3 / / Out - -------- /\\/\\/\\/\\ ------------- In- R4

Where R2 = R3 = 62 ohm R1 = R4 = 68 ohm

Vin -> 0.4Vp-p, Vout -> .125Vp-p, Rin = 47.2 ohm, Rout = 47.2 ohm

Cheers

PeteS

Reply to
PeteS
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I think CML is usually a unidirectional current sink, an open collector, pulling about 16 mA for the full-swing version, basicly an ECL sort of stage without the emitter follower. Some have an internal termination to Vcc, some don't.

Somebody correct me if I'm wrong.

Melanie may be able to do a direct connection, depending on the common-mode specs of the receiver. We need more detail.

John

Reply to
John Larkin

May I presume that Vref is +2.2V and the CML is open-collector pulling current through the 50 ohm terminations to make the ±400mV signals?

8mA alternating from each collector?

Can additional current be drawn from Vref?

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Well, you don't have long tranny lines and remote terminations on-chip! If you did, the chips would be toast.

Some of the CML parts, like a few of the GigaLogic things, have an internal 50 ohms to Vcc, so that if you terminate again, externally, you get logic levels of Vcc and Vcc-0.4.

I think "current mode logic" is a sometimes generic term, not precise like, say "TTL". (Just a little joke here.)

A couple of the Giga parts have pure current sinks that are externally programmable, all the way down to zero if you cheat a little, very clean and linear, 40 ps edges. That can be real handy.

John

Reply to
John Larkin

±400mV differential would imply an 8mA current source, steered by a diff-pair. But sometimes people get balled up in confusion about differential peak and peak-to-peak.

But 16mA _would_ give the conventional 800mV single-ended output.

I don't know what is the real spec, since I'm always on-chip and run as little as 150mV P-P differential... gotta keep those swings down when you're doing 3GHz ;-)

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Is the signal at the end of these "transmission lines" your specified ±400mV? Source and end termination _would_ account for the factor of

1/2 that John Larkin and I have been fretting over.

Does the far end have to terminate to Vref, or would 100 ohm differential suffice?

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

[snip]

Well! That's certainly clear as mud ;-)

Are the 50 ohm resistors on-chip or off-chip?

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Your observed signal swing. When you "source terminate" and then terminate the far end of the line you lose 1/2 of the swing.

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

[snip]

We think it's likely "standard" CML with a switched 16mA current sink, each 50 ohm would get pulled down 800mV. Add another 50 ohm in parallel ( the input impedance of the transmission line) and you get

400mV.

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Hi there,

I'm currently working on a board design and I have to interface two VLSI chips to each other that don't have exactly compatible level characteristics. To be more precise I have a differential CML output of U(t) = 1.8V +/- 0.400V * rect(t) being terminated 50 Ohm to Vref and a non-standard differential Input which assumes U(t) = 1.15V +/- 0.125V * rect(t) being 100 Ohm differentially terminated. I first thought about AC coupling but that only kills my DC part but doesn't come to solve the problem of incompatible swings. Maybe a resistor network would be the right choice but I am not so firm on that topic. Any help, suggestions and calculation examples would be appreciated.

Many thanks in advance and best regards,

Melanie

Reply to
Melanie Nasic

See...

Newsgroups: alt.binaries.schematics.electronic Subject: electrical interface problem - MelanieCML.pdf Message-ID:

for a possible solution.

(If you can't access the binary group let me know and I will post to a URL.)

This uses AC coupling.

If you happen to have the luxury of being able to adjust the current source in the CML output, I think this can be done direct-coupled.

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Hi PeteS,

thanks for your reply. I don't think that would work because the CML output stage "must see" 50 ohm transmission lines and I guess it would not be allowed to terminate them with 62 ohm in the middle?

Bye Mel

"PeteS" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

Reply to
Melanie Nasic

Hi all,

thanks for your fast reply. Vref is in fact +2.5V and I'm not sure whether CML is open-collector and how much current is alternating from each collector. Maybe a look at

formatting link
(page 103) will help but I am not so firm on those electrical specs. You would help me a lot by explaining that to me, though. :-) As transmitter I am using Xilinx' RocketIOs but their swing is higher than the maximum receiver swing (+/- 400mV instead of +/- 125mV) and the receiver is NOT supposed to exept some other common mode range than the 1.15 Volt (that's part of the specification: the goal is to achieve nearly exactly the U(t) given in my first mail). Many thanks in advance....

Regards, Mel

"Jim Thompson" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Reply to
Melanie Nasic

Hello Jim,

thanks for your support so far. The source termination is both lines 50 Ohm to Vref (CML) but the end termination should be 100 Ohm differentially. Where does the factor of 1/2 accrue from? The far end must not terminate to Vref but has to be 100 Ohm differential. As transmitter I am using Xilinx' RocketIOs but their swing is higher than the maximum receiver swing (+/- 400mV instead of +/- 125mV) and the receiver is NOT supposed to exept some other common mode range than the

1.15 Volt (that's part of the specification: the goal is to achieve nearly exactly the U(t) given in my first mail). Many thanks in advance,

Mel

"Jim Thompson" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Reply to
Melanie Nasic

What 50 ohm resistors (on-chip or off-chip) are you referring to, Jim? The CML transmitters have an internal 50 ohms to Vcc. And a question to John: I didn't understand why I get logic levels of Vcc and Vcc-0.4 if I terminate again externally? Where does the 0.4V come from? Or is it my swing that Vcc is high and Vcc-0.4 is low voltage level?

Thanks, Mel

"John Larkin" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Reply to
Melanie Nasic

--
So, no help offered, just more of your "Look at me, Ma" bullshit.
Reply to
John Fields

Okay then, all I got is a "standard CML driver" as described in

formatting link
and I want to interface to the receiver that is NOT supposed to exept some other common mode range than

1.15 Volt and voltage swing of +/- 125mV. How can this be achieved? I'm not a crack on this field so maybe you have to start be zero to explain to me. But first of all a quick solution would be better... ;-) Can or SHOULD I use a resistor network?

Regards, Mel

"Jim Thompson" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Reply to
Melanie Nasic

See Message-ID: in alt.binaries.schematic.electronic, subject "electrical interface problem" for a PDF on this discussion.

See if the schematic in abse is what you are thinking of. If so, then you might get by with an attenuator and a DC voltage divider. R4-R8 is the attenuator which provides 10.1 dB of attenuation. R7, R8, and R10 form the DC voltage divider. R9 is the terminator for your mystery device.

You can see in the simulation that your input common mode level is

1.15V and the signal level to the input (v(inp,inn))is 0.125Vpp. The equivalent power supply voltage running your 50 Ohm source resistors, VTTX, is 2.14 VDC which meets the Xilinx VTTX minimum supply of 1.8V.

Is this close to what you are thinking of?

--
Mark
Reply to
qrk

Since this is a xilinx related issue you might try to post this question to comp.arch.fpga where the xilinx folks hang out. Others have run into this and generally are very happy to give answers. There are people from xilinx there as well to answer questions.

Melanie Nasic wrote:

Reply to
none

What else do you expect out of him, John? he has to beat his chest at every chance to try to convince himself he's still worth something.

--
?

Michael A. Terrell
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Reply to
Michael A. Terrell

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