Random data generator...

You just have to write a Shift register with some XOR gates like a CRC generator. If you need speed use a SPARTAN3 OR Virtex-II -> a CLB can works like a quick small shift register -> special function of a Xilinx CLB. :-)

Laurent

David, decide whether you need true randomness, or whether pseudo-random is good enough. If it is, you can build linear-feedback shift register structures quite easily, and make them as long and as fast ( and parallel) as you want.

True randomness is far more complicated to achieve, is usually based >

The ITU-T specify some LFSR tap sets for use in test equipment. The O.150 series of specifications contains the information. These turn out to be the same as the ones in XAPP-052 for lengths 7, 15, 23 and

There are standard ways of unrolling the LFSR to make it parallel to achieve higher bit rates. 300MB/s isn't very fast for an FPGA though.

These LFSRs have been designed for testing *serial* data links. Experience gained when I was at Agilent indicated that they don't have enough transitions to properly stress wide parallel interfaces.

A combination of LFSR and an alternating all ones / all zeros pattern seemed ok.

Regards, Allan.

Lot's of simultaneous transisitions are good for testing against timing problems due to ground bounce, cross talk and the like. Another problem you should be aware of, is that for some circuits a random pattern with 50% propability for one and zero on each bit might not be a good test. A PCI core with 16 active bits in it's address decoder for example will only be selected once out of 64k cycles.

But one' can very easily produce random bit's of different propabilities: Just make the shift register longer and AND or OR together multiple shift register bits to produce a single output bit. AND3 for example gives you a 12.5% prob. for 1.

Kolja Sulimma