Lining up data...

I'm trying to implement a big MUX. This MUX will switch 6 bits of high-speed digital data along with its CLK @ ~ 300MB/s! There are 6 input ports and one output port. The output must contain the selected ports CLK (of course) as well as provide the selected ports data. I'm having trouble understnading how to make sure the data lines up at the output port! Timing simulations show a significant skew between data bits. I have a register at the output but that is not my problem. My problem is the path from the input pads tp the input of the register. I am using Foundation 6 / schematic entry because I am not up to speed in VHDL. (Yet) I have 7 STD MUX's on the page one for each data bit (0-5) and a MUX for the CLK's. All of the outputs according to the SEL lines provide data bits from ports 1-6 one at a time via the SEL lines. Any help would be great! I though about connecting the selected ports CLK to the EN pin of the input MUX's but I cant see how thats going to help with the data bit skew from bit to bit. I do not care if port 1 has a longer delay through the part (which I have not settled on yet) than any other port selected. How long it takes the data to get from the input pads to the output pads is of no concern to me because the data is DVI and the monitor will simply display what it gets when it gets it! Making sure that the data and the CLK is aligned all the way through the silicon seems to be very important.

Thanks,

Dave

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David Nyberg
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