Not that I know of. The closest is this:
Not that I know of. The closest is this:
-- Dirk http://www.transcendence.me.uk/ - Transcendence UK
Hi all
Is there a way to implement a true random number generator with logic gates ,nand nor FF etc without using white noise from a zener diode for example?
Thanks BarNash
es
?Something needs to be "noise based" instead of "logic based" for the result to really be random. Do you have any source of true randomness in the design?
Some all-digital chips make a bunch of different-length asynchronous ring oscillators and use them as data or clock sources to feed scrambler algorithms. The theory here is that the oscillators are subject to Johnson and shot noise effects, ambient temperature fluctuations, power supply noise, cosmic rays, metastability, whatever. One could easily put hundreds of ring oscillators on a modest FPGA.
I'm sure there are papers around.
google random number ring oscillator
I have a scheme where a pin of an FPGA is used as a relaxation oscillator node, similar idea.
John
NO.
Absolutely NOT close as the use of a zener /avalanche diode is present.
THAT "loophole" solution is more like it and with care, may do the job. How would one mathematically determine the distribution?
That's beyond my pay grade, but there are lots of papers; it seems to be a popular academic subject.
It would be tricky to just test the results on one chip, because some chips may have injection lock effects that others don't. One paper adds a randomness tester section to every chip just to check for that.
John
Feedback due to lateral PNP (if i remember correctly) action? If so, wrap an extra collector around the "generator" and ground that to kill the beta from (say) 10-3 to 10-6 or so.
by sampling the output.
gates
I made a pseudorandom noise generator for audio testing with a microprocessor based 32 bit two tap shift register. The processor is a PIC16F676.
The generator operates on a 4 MHz internal clock with a 77kHz chip rate. It produces a white noise sequence that is pseudorandom, not actually true random which is not possible in this kind of digital system.
Connected to the processor output is an RC network to convert the white noise sequence into "pink" noise for audio work.
If you are interested, I can give you the code and other details. Email me for details: nsmontassocatyahoodotcom. Remove the ns from the address start.
An interesting idea is to use the rule 30 cellular automaton (rule classification by Wolfram). This produces a high quality white noise with long cycle:
A client for which I'm working uses this algorithm in a DSP for multichannel decoherent white noise generators (multiple generator with different seeds) and with some additional software, switchable to pink noise. The device works very well.
Of course, it is not a true random number generator, because this is not possible with deterministic logic without some analog tricks, or by getting some entropy in complex systems with multiple interfaces to the analog world, like the Linux kernel does.
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
See the scope diagrams for signal samples and FFT spectrum:
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
"High-Speed True Random Number Generation with Logic Gates Only" by Markus Dichtl and Jovan Dj. Golic
For a short abstract see:
I haven't managed to find a freely downloadable version so for the full document you might have to pay.
There alse seem to be a number of patent applications out there.
Have anyone verified these claims over different FPGAs and medium scale or discrete gate implementations ? Has much happened after CHES 2007 ?
Gerhard van den Berg CSIR
"High-Speed True Random Number Generation with Logic Gates Only" by Markus Dichtl and Jovan Dj. Golic
For a short abstract see:
I haven't managed to find a freely downloadable version so for the full document you might have to pay.
There alse seem to be a number of patent applications out there.
Have anyone verified these claims over different FPGAs and medium scale or discrete gate implementations ? Has much happened after CHES 2007 ?
Gerhard van den Berg CSIR
"High-Speed True Random Number Generation with Logic Gates Only" by Markus Dichtl and Jovan Dj. Golic
For a short abstract see:
I haven't managed to find a freely downloadable version so for the full document you might have to pay.
There alse seem to be a number of patent applications out there.
Have anyone verified these claims over different FPGAs and medium scale or discrete gate implementations ? Has much happened after CHES 2007 ?
Gerhard van den Berg CSIR
No one has asked if he *needs* TRNG or if a CSRNG or PRNG will work, so a concrete design of a PRNG is premature.
Do you need a TRNG or will a a CSRNG (cryptographically secure random number generator) or PRNG (Pseudo random number generator) work?
What is the application?
"Anyone who considers arithmetical method of producing random digits is, of course, in a state of sin."
--John Von Neumann
Quoted in Chapter 3 of "The Art of Computer Programming" by Donald Knuth. Chapter 3 is devoted to random numbers.
-- Namaste--
Sampling is NOT a mathematical determination..
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