Thanks for the (late) praise. I was really proud of my drawing. :-) But it gets more complicated in BRAMs, what with the write and the read pulse dancing around each other. Still, food for thought... Peter Alfke
RAM in Altera EABs and Xilinx Block Rams
Jun 12, 2004
22 Replies
Rickman,
Not sure where you got this idea. Xil> Peter Alfke wrote:
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
You are responding to old messages. This has already been corrected by Peter and others. Thanks anyway.
Just FYI, I got confused between an edge clocked register and the data hold latch they have on the output. I am a visual guy and the app note is mainly words which can get me confused sometimes.
-Rick "rickman" Collins
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