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Rad-hard (neutron/SEU and space) tutorial?

Does anyone know of something more like a "how to" or real design guidelines for designing rad-hard systems, for system/board-level (ADC, DAC, power supplies, etc) design, as well as for FPGA and ASIC hardware?

I've found a lot of information around that gave specific numbers about some chips, but I wasn't able to actually understand what the reports were saying. I know that for an FPGA, I should either use a flash or antifuse based chip, or otherwise use a chip with configuration CRC checking and reloading, but how do I select parts like power supplies, ADC/DACs, and RAMs? Even if my FPGA or ASIC design is solid, I'm worried that I'm going to end up shooting myself in the foot on the rest of the system.

And for FPGAs and ASICs, what are the design considerations? How would I implement a voting circuit for triple-redundancy in general? And how would I avoid the possability of an error in the voting circuit?

Also, if anyone knows of any good books, papers, courses/classes/training, or even consultants, please let me know.

Thanks, Mike

Reply to
MikeD
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Mike,

Wow. Not a small request.

A few suggestions:

  1. Read all papers from MAPLD, RADECS, NSREC, and SELSE.
  2. Get an IEEE subscription to their e-library and read all the single event effects papers
  3. Read all the online information from Xilinx
  4. Take the TMR Tool(tm) class from Xilinx: this is the only automatic tool which has been tested in a particle beam and shown to actually WORK. TMR Tool creates a functionally correct TMR with triplicated voters for all feedback paths automatically. (Not a trivial task, and easy to mess up and fail if you do it by hand)
  5. Ask your local Xilinx FAE to present the SEU modules for V43 and V5 to you.

If the above seems a bit daunting, well, it is.

Continuing,

  1. Search USPTO site for all patents on "single event upset" patents for circuit techniques for mitigation (if you are an IC designer, so you don't infringe on Xilinx patents).

Some links:

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or
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or
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...to show but a very few.

Oh, and google for "Austin Lesea" "soft error" (only 157 things there to read).

Austin

MikeD wrote:

Reply to
Austin Lesea

I would say the best place to find help, courses and consultants is the yearly MAPLD conference, there you will find all the SEU junkies :-)

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Hans

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Reply to
Hans

Hi,

MikeD schrieb:

For systemlevel actually no free available howtos, sorry. For FPGA/ASIC, you get information on the websites of the vendors.

You will typically have a client, when developing a radhard circuit. First read the requirements from your client. It's a big difference, if your circuit is designed for a mission on Mars or if you need to build equipment intended to be active for 15 years in GEO. In general it could be said, that only fuse based fpgas are acceptable for the second scenario, while you could achieve the first with nearly every fpga. The easiest way to achieve a rad hard fpga design is by using an Actel RT device with a "normal" rtl code. Your design should be bullet proof against deadlocks occuring due to any SEU, which is a good advice for every design, but a necessary condition to sell a rad hard device.

Again depending on your requirements. Do you need only to be rad-hard against a total dose? Then search devices with given total dose and check wheter this device matches the required total dose. Do you need to be stable against SEE? Thats a bit harder. If you purchase rad-hard devices, you will get a lot of information regarding behavior of this device under radiation. You have to read, understand and verify, that your system accepts this behavior for each devices. E.g a OPAmp might have a transient after hit from a heavy ion, if this opamp feeds your reset circuitry, than you have to deal with this transient by:

  1. selling it as a feature
  2. removing any unintended influence of this transient

Your client will likely accept a shortterm loss of data, but can't accept a loss of equipment. bye Thomas

Reply to
Thomas Stanka

Product line of ACTEL Radiation Hardened FPGA's line :

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RH Design considerations :
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About voting circuit :
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Regards, Krishna Janumanchi

MikeD wrote:

Reply to
krishna.janumanchi

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