Questions about multiple rom instances in Quartus II

Hi John,

You will need to expose the parameter that is used for the .hex initialization file. The MegaWizard-generated Verilog file will have a line saying defparam .INIT_FILE = "foo.hex"; that parameter needs to be added to the MegaWizard-generated module and passed down. Then assign a unique value for that parameter to each instantiation of the wizard-generated ROM sub-module.

As for the question on inversions: all our blocks have programmable inversions on the inputs, so we allow inverts to be absorbed across hierarchy boundaries. The solution would be to insert an LCELL buffer to prevent the programmable inversion being propagated.

Where the code has

wire inverted_signal;

You will need to add

wire buffered_inverted_signal;

lcell lcell_inst (inverted_signal, buffered_inverted_signal);

and this will prevent the inversion propagating. However, It will use up an LE.

Hope this helps,

Subroto Datta

Altera Corp.

I've already tried using defparam (without adding it to the top file) and got: Error: Verilog HDL or VHDL error at c18m.v(78): Unconverted VERI-2009: no support for cross-hierarchy defparam id c.RS.m.altsyncram_component.init_file

Tomorrow I'll 'expose' the parameter. Also, Verilog 1995 didn't support string parameters; is that the problem?

Thanks a lot!

-John

Hi John,

The reason for the error message is that you are trying to use a cross-hierarchy defparam, which means setting aparameter on an instance several levels deep in the hierarchy. That is not supported today -- you can only set parameters on a module you are instantiating, not on any of its children. Instead, add a new parameter to the megawizard wrappper and pass that down. An example of a modified altsyncram file, with the edited lines marked with // EDIT. is shown below:

Here is an example of what needs to be done:

// megafunction wizard: %ALTSYNCRAM% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram

// ============================================================ // File Name: my_altsyncram.v // Megafunction Name(s): // altsyncram // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 5.0 Internal Build 111 02/14/2005 SJ Full Version // ************************************************************

//Copyright (C) 1991-2005 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details.

// synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module my_altsyncram ( data, wren, wraddress, rdaddress, clock, q);

parameter my_hex_file=""; // EDIT

input [1:0] data; input wren; input [3:0] wraddress; input [3:0] rdaddress; input clock; output [1:0] q;

wire [1:0] sub_wire0; wire [1:0] q = sub_wire0[1:0];

altsyncram altsyncram_component ( .wren_a (wren), .clock0 (clock), .address_a (wraddress), .address_b (rdaddress), .data_a (data), .q_b (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .data_b (2'b11), .q_a (), .rden_b (1'b1), .wren_b (1'b0)); defparam altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.width_a = 2, altsyncram_component.widthad_a = 4, altsyncram_component.numwords_a = 16, altsyncram_component.width_b = 2, altsyncram_component.widthad_b = 4, altsyncram_component.numwords_b = 16, altsyncram_component.lpm_type = "altsyncram", altsyncram_component.width_byteena_a = 1, altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.indata_aclr_a = "NONE", altsyncram_component.wrcontrol_aclr_a = "NONE", altsyncram_component.address_aclr_a = "NONE", altsyncram_component.address_reg_b = "CLOCK0", altsyncram_component.address_aclr_b = "NONE", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", `ifdef NO_PLI altsyncram_component.init_file = "foo.rif" `else altsyncram_component.init_file = my_hex_file // EDIT `endif , altsyncram_component.intended_device_family = "Stratix";

endmodule

// ============================================================ // CNX file retrieval info (lines remobed below) // ============================================================ ..... // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "foo.hex" // ... // Retrieval info: GEN_FILE: TYPE_NORMAL my_altsyncram_wave*.jpg FALSE

With regard to your question on string parameter: Verilog 1995 does support string parameters, so this is not an issue.

Hope this helps, Subroto Datta Altera Corp.

"John Rible" wrote in message news: snipped-for-privacy@enews4.newsguy.com...

Subroto-

Tried it LATE last night. It works. And now the error message makes sense; is this difference from the Verilog LRM documented anywhere?

Thank you,

-John

Subroto Datta wrote:

...snip...

Hi John,

In case you don't have the code all sorted yet, here's a tutorial on how to change the megawizard generated module to pass down the hex file parameter you need (thanks to one of our megafunction gurus):

You need to parameterize the wizard generated blackbox module. By default, the wizard generated module is fully customized according to the user selection in the wizard.

If you need to instantiate multiple instances which are variations of a base module, you can parameterize the variation in the base module.

For example, the following would be a typical wizard generated ROM module.

module myrom (

address,

clock,

q);

input [4:0] address;

input clock;

output [7:0] q;

wire [7:0] sub_wire0;

wire [7:0] q = sub_wire0[7:0];

altsyncram altsyncram_component (

.clock0 (clock),

...

...

.q_a(sub_wire0));

defparam

altsyncram_component.operation_mode = "ROM",

....

....

altsyncram_component.init_file = "test.mif",

....

You can parameterize the above module by changing it to the following (I highlighted the change in red)

module myrom (

address,

clock,

q);

input [4:0] address;

input clock;

output [7:0] q;

parameter mif_file = "test.mif";

wire [7:0] sub_wire0;

wire [7:0] q = sub_wire0[7:0];

altsyncram altsyncram_component (

.clock0 (clock),

...

...

.q_a(sub_wire0));

defparam

altsyncram_component.operation_mode = "ROM",

....

....

altsyncram_component.init_file = mif_file,

....

And now they can instantiate the instance with different mif_file on the upper level source.