Reusing code (Altera Quartus II 3.0)


I am a relative "n00b" with regard to FPGA-programming, but I'm currently working on a Rijndael-implementation on a APEX1A dev.board. And I have run into some problems.

I want to put my top-level design together from several smaller building blocks, that I want to design, compile, simulate and "forget". So when I need them later on, I'd like to simply import them into my design.

The only way I have managed to do this so far, is to copy the design- files from their original location, and into my new project directory. And this clearly isn't very efficient or simple.

I know there has to be a simpler and better way, but I haven't benn able to figure it out yet. So all suggestions would be greatly appreaciated.


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There are several approaches based on different levels of complexity.

The simplest one

  1. Create each block as a Quartus project in its own directory.
  2. Create a symbol for each block. Use the File Create/Update Symbol Files for Current File command. This command also creates Entity/module definitions that can be referred to in other HDL files.
  3. Next create a project called "top" where you can stitch all these different symbols together into a single schematic (bdf file), using the Quartus Block editor. Another alternative is to stitch them together using a Verilog or VHDL file.
  4. To compile this "top" project you will need to Create User Library Entries that points to each of the directories that contain the separate blocks. This is needed so that the source files of each of these blocks can be found during netlist extraction and synthesis (quartus_map), at the start of the compile. The User Libraries setting can be found from the Assignment->Settings->Files and Directories->User Libraries dialog.

One word of caution: This approach requires that you do not have entities/modules with the same name in different User Library Directories. If you do have entities/modules with the same name in different directories the extractor will find and use the first reference only which is not what you want.

  1. Next add the root level VHDL and Verilog Files for each block to the "top" project. This is done from the Assignment->Settings->Files and Directories->Add/Remove command. This is not needed if you have followed the convention that each entity/module is in a HDL file with the same name.

  1. Compile the "top" level project. If the software says that files cannot be found this means you have missed something in steps 4 and 5.

- Subroto Datta Altera Corp.


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Subroto Datta

Thank you so very much, Subroto Datta. I had partly managed to figure out how to do it, but you put the final pieces in their places. So thank you once again.

It is such a luxury to be able to get expert help, from such a broad variety of skilled engineers that frequent this news group.

Respect to all of you :-)


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