I am a relative "n00b" with regard to FPGA-programming, but I'm currently working on a Rijndael-implementation on a APEX1A dev.board. And I have run into some problems.
I want to put my top-level design together from several smaller building blocks, that I want to design, compile, simulate and "forget". So when I need them later on, I'd like to simply import them into my design.
The only way I have managed to do this so far, is to copy the design- files from their original location, and into my new project directory. And this clearly isn't very efficient or simple.
I know there has to be a simpler and better way, but I haven't benn able to figure it out yet. So all suggestions would be greatly appreaciated.