Hi, Here is a hypothetical question. I have FF with 50ps of setup time,
10 ps of hold time; however this FF has 200 ps of clk - Q delay. I want to use this FF to capture an 8Gbps input stream (125 ps). Is this possible ( mainly due to CLK-Q delay) ? I am open to using advance techniques like pipeline timing etc.
The NBSG53A can clock to >8 GHz, so presumably propagates data at that rate. Typical setup/hold is 10/7 ps. You might consider interleaving 2 or 4 of these to let their outputs settle long enough to pass the data on to the rest of the system.
Tricky stuff, at this speed. These parts are so small it's hard to keep the trace impedances matched as the traces neck down into the chips. Think *very thin* dielectrics.
Maybe so, but I'm not brave enough to use vias below about 200 ps. If you TDR a matched line that hops through a via, it usually look like a lumped capacitor. I guess it's possible to keep a via at the characteristic impedance somehow, but we just try to keep all the fast sigs on the top layer. For complex logic, that would be impossible, but we've never done that.
We're just now doing a fiducial pulse generator that drives an e-o modulator. It uses a GigaLogic gate to make a fast (40 ps) edge, then differentiates it into the input of one of the Giga parts that has variable output swing (we DAC that) and then through two GaAs distributed amps. We're getting a clean 100 ps impulse variable from 0 to almost 7 volts, all on FR4 with a 10 mil first dielectric layer, necking down the 50 ohm traces into the rediculously small chips. It all gets hot.
Can't you via down to the next layer somewhere before the bottleneck and then use a plane above and below instead of just below? The transition may be a bit nasty but should be feasible.
Wow. Is it Onsemi GigaComm? These are really expensive but if it's high-end they are sure nice devices to have at hand. I rarely designed at that kind of budget level so fast stuff had to be discrete. But it wasn't this fast.
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