Progress in FPGA static Icc timeline degrade

In 2003, Xilinx was saying higher static power was an inevitable price of progress, and that speed was king, and nothing was on the Horizon to solve this.....

It is interesting to read this latest press release

formatting link

"By using three different thicknesses of the insulating gate oxide layers, the companies were able to break the traditional tradeoff between power consumption and performance, and expect to lower static and dynamic power consumption by 50 percent from previous generation devices with the Virtex-4 platform FPGA family."

Some real numbers would be nice : Just where are we now (V4 samples), on the static power spectrum ?

'50 percent' is not great, but is much better than another step in the wrong direction :)

and also this, which is more on the horizon @ 65nm:

formatting link

seems the foundries/R&D are very aware of the importance of static Icc in many applications, and they are working to tune the process to allow designer selection. Cutting edge silcon EDA tools now talk about 'power closure', in the same way timing closure was the hot button a couple of years ago.


Reply to
Jim Granville
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.