Is FPGA fully static?

If i wish for debuging purposes lower clock frequency that i supply for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz external clock source and for debuging purposes i will supply 40 Hz clock, does circuit behave exactly as on higher speed expect that all happens 1 000 000 x slower or is this situation more complicated?

regards, Raivo

Reply to
Raivo Nael
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The DCMs in Xilinx parts have a minimum frequency requirement, it's in the neighborhood of 25MHz. If you want to use a slow clock you can't use the DCMs, you will have to use the input clock directly.

Reply to
B. Joshua Rosen

If you do NOT use the DCM, you can go as low as you want. The DCM has a min input frequency of 25 MHz,( except for the FS mode where the min output frequency is 25 MHz, and the input frequency can then be significantly lower).

Peter Alfke, Xil>

Reply to
Peter Alfke

The older Xilinx FPGAs that didn't have clock multipliers and DLLs are totally static. You could clock them with a debounced pushbutton if you wanted to. I think even the current ones can be used like this, but you have to avoid the PLL and DLL components, as they do have a specified min and max frequency.

I have several products that run Xilinx FPGAs WAY below their maximum clock frequency, because that is all the speed needed in the application. I have a device I'm debugging right now using an older 5V Spartan chip that has no continuous clock whatsoever. There are a few clocks that are really strobes from other devices, but the part is largely combinatorial. It routes signals around unpopulated bus slots in a piece of gear, reports which slots have what boards in them, if any, and such things.

Jon

Reply to
Jon Elson

There is a caveat on the older devices: The 4000 series had a limitation on the amount of time the clock could be held high to CLB RAM due to power dissipation concerns. I can't remember now if that included the 4000E series or not, I don't think it did but am not sure. So while those particular devices were static, you had to be careful not to park the clock high if you had any CLBRAMs in your design.

Other than that, and the DLL/DCM restrictions others have mentioned, there is no minimum clock.

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Reply to
Ray Andraka

FS mode?

Ken

Reply to
Ken

Reply to
Peter Alfke

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