WYSIWYG option in xilinx webpack 6.3

wysiwyg effects the place and route,or the logic asignment in the case of a cpld and in this mode the logic is not minimised or refactored which means that in most cases the logic is faster than a design which has had a lot of reduction and refactoring performed. The compiler producing 'wrong code' isnt effected by how much logic optimisation is performed I suggest you look elsewhere for the cause of your problems.

Maybe i'm dreaming...

This is the VHDL code with the interesting 4bit counter ptc:

if (prc = 7) then hf2

cause of

It's kind of hard to tell. I assume the unrelated signal you are talking about is iff1(4).EXP. I do not see it in the exerpt, but it might be an intermediate term that is generated in another macro-cell that is a function of the HDL. Did you do a functional simulation of the logic? Does the post synthesis design simulate as expected for both the wysiwyg and non wysiwyg. Are there any synthesis warnings concerning latches. Transparent latches are usually undesirable. Are you getting logic failures in hardware that could be speed related, cause I would guess that the wysiwyg could possible be slower.

Good-luck

-Newman