Power-up input value detection

Hi I am working on a design involving the cloning of an obsolete chip in an FPGA (Altera EP10K family). The behavior of the chip depends on some input values "at power-up" (no mention of any reset there). My problem is to reliably detect power-up.

I could still manage something with the reset condition but that's not exactly what the datasheet says ("If is strapped Low at power-up...")

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Reply to
Nicolas Matringe
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How long are the "power-up values" stable? The EP10K has a stabilization time that will need to be taken into account and compared against your old part.

Reply to
fabbl

What do you think "at power-up" means?

Most chips I've worked with have a separate reset signal that must be held active until the power is stable. "at power-up" really means when reset goes away. It's the designer's job to make sure that doesn't happen before power is stable.

Usually the signals you are looking at are not "strapped" (or the problem would be simple) but there is a weak pullup/down that is strong enough as long as no real driver is driving that signal but doesn't add much load to mess up the normal use of that pin. So the other half of the designer's job is to make sure that nothing else drives those signals until the chip has come out of reset.

Sometimes that last paragraph is wrong. If you are loading the FPGA from a uProc, the uProc might have control of those signals so the software has to get it right rather than using pullups/downs.

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Reply to
Hal Murray

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