Let's say I have a pull up resistor in series with a 5V source and a switch to ground, and this feeds into an inverter IC such that when the switch is closed the input is connected to ground otherwise when the switch is open the input goes to the resistor and the 5V
Does it matter if my pull up resistor is 1K, 10K, or 100K? I mean, I guess it needs to limit the current going into the input so is the bigger the better? How do I pick it, or does it really even matter (besides limiting the current going into the IC input)
If it's CMOS, it is, for all intents and purposes, simply a capacitive load, so the pull-up value only determines rise-time. If you have hysteresis ('HC14) there's one answer, otherwise another ;-) ...Jim Thompson
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The important consideration in this case is the ratio between the source resistance (the pull-up resistor) and the input impedance of the inverter. If the input is purely resistive, then that ratio determines the voltage drop, because input and pull-up form a simple voltage divider. If the input is reactive, then the ratio determines the rise or decay time, and hence the pole or zero frequency. Basically you need to consider the pull-up as part of a filter, and look at your timing and input voltage requirements.
So, low enough for the speed and voltage level you need, but no lower or, as you note, you'll be passing more current you need through the pull-down device.
Being new to digital, I thought the 10:1 rule of thumb might work. As it happens, there seems to be standard levels and impedances, so I copy what appears to be common practice from data sheets.
CMOS gates have super high input impedance, so most anything will pull them up. TTL pulls itself up, so technically it doesn't need any pullup at all; you can get away with none in most situations.
A very high impedance node, like say CMOS with a 1M pullup, could be sensitive to stray electrostatic or line-frequency hum. 10K is good insurance. Pulling up TTL will increase noise margin, too. If there's much wiring between the switch and the logic, a capacitor to ground, or a more elaborate input circuit, is a good idea.
There's no need to "limit current into the input" as neither TTL nor CMOS has significant current into a pulled-up input.
Actually the on-resistance of the fet pulling down the resistor is what matters. At some point, you will not pull low enough to trip the input gate.
***Well, I said I'm new to digital. Thanks for the correction.
***What fet? I can't see where the OP mentioned that. How does the on resistance of whatever fet you mean compare with a typical pull-up resistor of, say, 3.3k?
***I'm afraid I'm really confused now. Perhaps you could give an example to illustrate what you mean?
For every pull up, there is a pull down. Generally the port that needs a pull-up has an open drain nfet. The resistor does the pull up, the n- fet does the pull down. Usually you find pulled ups on wired-or lines, or some sort of level shifting.
The pull down device has to be strong enough (low enough on resistance) to pull down the line sufficiently so that whatever is sensing the line recognizes the signal as logic zero.
There are other reasons for a pull up, but I think I more information might just lead you astray. However, you often find pull-ups in power on reset circuits. This is because a resistor will provide a current path under any supply condition. As you power up a chip/system, active devices (p-fets generally) will not be able to pull high until the supply voltage reaches at least a VT of the P-fet. A pull up resistor on the other hand starts to source current as soon as the power supply is not zero (presumably positive). Power on reset, if done well, can be tricky. It is often the death of board level designs versus a well designed chip. For simple logic circuit, you can probably get by with a crappy power on reset. For something like a switching supply, if the power is designed poorly, the device can self destruct.
I completely agree. Ever since I was a kid, it's easy to spot those 4.7K carbon comp resistors. They're the jelly beans in my parts bins.
To the OP - you need to know how much current the inverter input will draw (flowing into the input) when the switch opens because this will reduce the voltage to the inverter input. The speed at which the voltage will rise (just after the switch opens) depends on the value of the resistor and the capacitance of the inverter input, but you're probably not worried about that (just a guess).
Bob
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Smart Tweezers to the rescue. Not as nice as proper markings, but really good for finding board stuffing errors.
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We've seen that too. It's not a date code, rather some sort of manufacturer's code. It does allow us to verify that the proper component is stuffed but not much more.
If a switch is operated at very low current the contact surfaces can become contaminated with a thin layer of oxides and insulating organic deposits. Using a reasonable sensing current tends to break down this layer, giving better reliability. A capacitor - perhaps 100nF - across the switch contacts allows a "large" current pulse when the switch is closed which is helpful in keeping the contacts clean.
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