PXA270 Power-up sequence

I'm looking for information about the power-up sequence of a PXA270. Working in production, I have beaucoup boards that do not power-up, aka do NOT boot. Is there any reference material that decsribes this process and what hardware attributes the device needs before it can boot??? Another question, could the JTAG interface provide the status of the device before it boots??? Any and all assistance would be Greatly appreciated. Respectfully Brooklyn Bob

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You _have_ looked at the Intel website? Usually this sort of thing is all over such sites.

While you're looking, see if there's a reference design out there. In theory a reference design from the chip manufacturer will have everything that a production design needs; many manufacturers treat the reference design as the de-facto standard of how to use the chip.

Possibly, depending on where the process is failing.

I'm not familiar with that chip specifically, but the normal power-on sequence for any processor is:

Power is applied while (hopefully) the reset is active. During this period the processor clock source starts up and stabilizes, and the processor recognizes the reset. Some processors will latch the reset and hold themselves in reset as long as necessary; other processors will need to be held in reset by external hardware for some minimum number of clock cycles, yet other (simple) processors will synchronously reset all their internal logic in one clock tick (don't count on _that_!).

Out of reset, the processor will be in a known, defined state. It will start executing code out of some specific location in it's memory map. That code will be responsible for setting up the processor for the specific application, then finally it will branch to some sort of application code, never returning to boot code until the next power-up or some exceptional circumstance.

_If_ your processor is resetting correctly (and they don't always) then you can use JTAG to check the start up code. Checking the reset circuit operation can be done with an oscilloscope and (_not_ or) perhaps a logic analyzer; it should be done unless you are 100% certain that the reset is happening correctly (and no glossing over this if you're only 99.44% sure

-- if the processor is flubbing the reset it may start executing code before it stumbles into the badly initialized hardware).

I'd plug the JTAG into a working board to make sure that I can query the processor state while the boot-up code is running, then I'd try it on a bad board.

Keep in mind that whatever is happening pretty much has to be a susceptibility to hardware variations -- if it weren't, you wouldn't have some good boards and some bad. I'd be looking for circuit problems (hence my screed about resetting), timing problems (Does this thing interface directly to SDRAM? Is it as flexible and byzantine as the Freescale MPS860?), and uninitialized variables. Note that timing problems could either be in hardware or they could be some race condition in the software bring-up process.

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Tim Wescott

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