I've dealt with:
- "Regular" PLL's where there's a VCO and a phase detector and a loop filter and the frequency is slewed to phase-lock the VCO to a reference.
But I also occasionally deal with:
- Clock-recovery circuits that don't really have a variable-frequency oscillator. There is a clock, but it's fixed frequency and typically runs 8x or 16x (or sometimes more) higher than the data rate. There's a shift register and a clock-pulse recovery subcircuit, and the the shift register has its phase adjusted +/- a clock or two to keep the data separator locked to the data.
Is #2 a PLL? It is phase-locked, but doesn't really have a variable frequency that "remembers" the last time it was locked (in the absence of a data stream it ticks along solely according to the fixed-frequency clock without any adjustment).
I have sometimes seen things like #2 called a "digital PLL" but my gut feeling is to call it a "data separator".
And there's a third category:
- A digital PLL with a "numerically controlled oscillator", e.g. frequency really is being adjusted (not just phase), but it's all done with counters instead of a VCO.
Maybe #3 is a true "digital PLL".
Am I too picky about nomenclature?
Tim.