Hi, I have a design in which I need to instantiate two microblaze system instances (the same microblaze system in two places). I'm doing it by the following way:
1) I've created a system containing a single microblaze (in EDK) 2) I've instantiated it in my hdl code in two different places. 3) Then I merged the two bmm files into a single bmm file which looks like this://///////////////////////////////////////////////////////////////////////////// // // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // ///////////////////////////////////////////////////////////////////////////////
ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;
/////////////////////////////////////////////////////////////////////////////// // // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // ///////////////////////////////////////////////////////////////////////////////
ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;
4) I synthesize my design using synplify 8.1 5) I call the following script (for translate and map)ngdbuild -a -p XC4VLX80-FF1148-10 -bm /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm
-sd ../../../../syn/syn_v4/edf
-uc ../../bs_lx80.ucf bs rev1/bs.ngd;
map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf;
The ngdbuild goes well but the mapping process has lots of errors ( it seems that the mapper tries to place the two microblaze instances on top of each other) part of the map log file (.mrp) is attached Can you please advise ? Thanks in advance, Mordehay.
Snippet of the map report file (originaly conatins 465 errors):
Release 7.1.03i Map H.41 Xilinx Mapping Report File for Design 'bs'
Design Information
------------------ Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf Target Device : xc4vlx80 Target Package : ff1148 Target Speed : -10 Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ Mapped Date : Mon Nov 6 11:55:10 2006
Design Summary
-------------- Number of errors : 465 Number of warnings :3074
Section 1 - Errors
------------------ ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y1) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y2) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y3) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y0) which require the combination of the following symbols into a single SLICE component: LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y4) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y1) which require the combination of the following symbols into a single SLICE component: LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read) LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y5) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y2) which require the combination of the following symbols into a single SLICE component: LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y6) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y3) which require the combination of the following symbols into a single SLICE component: LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read) LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y7) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y4) which require the combination of the following symbols into a single SLICE component: LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) LUT symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) LUT symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y8) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X2Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y9) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol
"CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =
CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) RAMDP symbol
"CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =
CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. and it continues like this ....