Hello, So, I am in the process of working on a new project where we will be using PCI Mezzanine Cards (think normal PCI cards from your PC, except in a smaller form factor) for a small, expandable, embedded system. This system will be running stand-alone (no CompactPCI or other backplane scheme). Just a Processor PMC card running the show, as well as a few add-on PMC cards on a stand-alone carrier card.
I have come up to speed on PCI in general and feel that I understand how the bus is enumerated, how transactions take place, etc. The one thing I don't get yet are the interrupts (Note: I come from the embedded world, so I understand interrupts in the general sense, but not how they apply to PCI).
In all the timing diagrams shown for PCI, you never see any indication of the interrup lines being used (INTA-INTD are available on the PCI bus). The typical (watered-down) transaction goes like this:
0) PCI initiator device asserts its request line 1) PCI system arbiter asserts the initators grant line indicating that it can use the bus 2) PCI initiator puts a 32-bit address onto the bus 3) PCI target device (that has the 32-bit address as part of its memory space) indicates that it is being targetted by asserting the "device select" line 4) PCI initiator starts clocking 32-bits of data on to the data bus 5) PCI initiator asserts the "stop" line synchronous with the last 32-bit data element...and the transaction is basically complete. At this point, the PCI interface hardware at the PCI target end would now have buffered up the bytes that were sent by the PCI initiator, and the PCI target hardware would then signal to the CPU at the target end that data has been received over PCI, and some device driver would then suck the data up into software-land for processing.
But how does INTA fit into this whole thing? You typically see the INTA line of an non-monarch PCI device (the one that doesn't enumerate the bus and is an interrupt generator) hooked up to one of the INTA through INTD lines on the monarch PCI device (the one that does enumerate the bus and is an interrupt receiver) to allow a direct interrupt from non-monarch to monarch. Does the initiator device not need to generate interrupts at all in the above scenario? This is my leading argument, since I have read that interrupts aren't even required. Is the idea here that a PCI initiator can use interrupts (INTA) to signal to a PCI target if it needs to do some sort of expediated transaction? If so, then does the INTA line get asserted prior to the transaction? This doesn't really make any sense to me, because the CPU shouldn't be interrupted and have to wait while the transaction completes.
I'd appreciate any insight here...thanks for reading!
Regards, John