Planes are shorted by their parallel-plate capacitance, as well as any additional vias and bypass caps. For, say, a 1 ns risetime edge, the amount of pcb plane that matters is in the ballpark of a square foot... tens of nanofarads. And within that square foot or so, there are going to be LOTS of bonus vias and bypasses. A couple of pF per inch of trace capacitance sees this structure as a dead short. Proper planes are equipotential as close as doesn't matter. The entire plane structure is the "return path."
If your planes *aren't* HF equipotential to 100 mV or less, you've screwed up a number of things. If they are, a signal can't distinguish between them as "reference planes."
Of course: there's always crosstalk between nearby signals.
Words, not theory. Theory needs numbers.
This gadget accepts an OC-3 optical payload, phase-locks to it, picks out triggers, and generates eight delays of up to two seconds each, with 1 ps resolution. Relative jitter between channels is around 3 ps RMS, and between two separate boards around 6. It has a uP, optical receiver, a PLL, two FPGAs, and all sorts of nasty stuff, including a bunch of Eclips Lite ecl, running mostly in PECL mode, where the ecl logic reference is +5V. It was laid out entirely with disregard for return current paths.
John