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Bypass capacitors placement for regulated output

Hi,

Please refer to the schematic at the link below.

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This is part of the reference schematic from Freescale. All the pin names starting with DCDC are regulated voltage outputs from the MCU's internal voltage regulator.VDDD, VDDM, VDDIO_P are power supply inputs to the core, memory and IO. This MCU takes single 5V and generates different regulated outputs to be connected externally to the VDDD, VDDM and VDDIO_P pins.

I looked at the PCB layout files (Gerbers) provided by the vendor. The bypass capacitors 0.01uf, 0.1uf, 1uf and 33uf for each DCDC regulated outputs are placed in such a way that 0.01uf is placed closest to the pin, next 0.1uf, next 1uf and finally 33uf litlle away from the respective pin. This placement, if I am correct, is ideal for IC power supply inputs VDDD, VDDM and VDDIO. Since DCDC pins are outputs supplying power, shouldn't the order be the otherway? Also, the schematic has more bypassing for output pins than for the input pins.

Any help in understanding the logic behind is greatly appreciated.

Thanks in Advance.

-mjnk

Reply to
Mahen K
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There is no logic. The idea of paralleling a bunch of different-value caps is almost always a silly affectation. A single 1 uF 0805 or 0603 cap per pin is plenty. IC appnote authors aren't paid very well, so they hustle kickpacks from capacitor manufacturers.

I've heard of people using hundreds of bypass caps per FPGA. We typically use six, and have never had a power problem.

I saw one board being stuffed on an automatic p+p machine that had over 3000 bypass caps. I knew one guy who didn't use bypass caps on logic boards at all, and his stuff worked fine. Plane-plane capacitance was enough.

John

Reply to
John Larkin

..

John,

Thanks for quick response.

My question is on the order of placement of the bypass capacitors at the output and the reason behind bypassing with more caps at the output than at the input.

-mjnk

Reply to
Mahen K

John Larkin schrieb:

Hello,

it depends on the type of logic used. A logic with a constant current consumption like ECL may work well without bypass caps. What type of logic was used on the board with more than 3000 caps and what on that other board without bypass caps at all?

Bye

Reply to
Uwe Hercksen

The big board was part of a memory test system, full of custom stuff, so I don't know what the logic was. The "no caps" guy used a lot of MSI TTL type stuff. Some of the Xilinx appnotes suggeat insane numbers of caps, mostly based on silly Spice models.

On a multilayer board with power and ground planes, the planes are the real bypasses. A scattering of 1 uF ceramics will take care of lower frequency bumps. Of course a chip like a Pentium that goes from 1 amp to 40 amps in millisecond blips will need serious low-frequency stiffness.

An hour or two spent TDRing real boards is a revelation.

John

Reply to
John Larkin

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