Please refer to the schematic at the link below.
This is part of the reference schematic from Freescale. All the pin names starting with DCDC are regulated voltage outputs from the MCU's internal voltage regulator.VDDD, VDDM, VDDIO_P are power supply inputs to the core, memory and IO. This MCU takes single 5V and generates different regulated outputs to be connected externally to the VDDD, VDDM and VDDIO_P pins.
I looked at the PCB layout files (Gerbers) provided by the vendor. The bypass capacitors 0.01uf, 0.1uf, 1uf and 33uf for each DCDC regulated outputs are placed in such a way that 0.01uf is placed closest to the pin, next 0.1uf, next 1uf and finally 33uf litlle away from the respective pin. This placement, if I am correct, is ideal for IC power supply inputs VDDD, VDDM and VDDIO. Since DCDC pins are outputs supplying power, shouldn't the order be the otherway? Also, the schematic has more bypassing for output pins than for the input pins.
Any help in understanding the logic behind is greatly appreciated.
Thanks in Advance.