CMOS LVC bypass & design practices

CMOS LVC can generally be bypassed the same way, although if you have fast bus drivers, you may well need much more (but that's true of all the logic families for that application).

As to design practise rules

  1. Never leave an input floating (unless the mfr has stated it's ok because there's an internal pull (up | down) that takes the pin to some default state.

  1. Make sure your input pulses aren't slow rising unless you are using a trigger type input.

  2. Watch your output capacitive / resistive load - CMOS tends to be somewhat more sensitive to those issues, in my experience.

Your mileage may vary, of course.

Cheers

PeteS

Reply to
PeteS
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SMT capacitors perform better than thru-hole types, because the ESR, ESL are lower due to the smaller physical package. ~ Use a ground plane if possible. ~ If a ground plane is not possible keep the area of the loop through which the bypass current flows as small as possible. Inductance is directly proportional to loop area. ~ Keep connections to the cap as short as possible to minimize series inductance.

Reply to
Jon

This is simple:

Use a multilayer board with a solid ground plane layer and a solid Vcc layer, but the Vcc layer can be reasonably chopped up into pour areas if you have multiple voltages. Multilayers are cheap nowadays.

Keep the dielectric thin (.005 inches, maybe) between Vcc and ground planes.

Each IC has vias to Vcc and ground, close to the pins.

Scatter a modest number of surface-mount 0.1 to 1.0 uF caps, 0805 or

0603 size, around the board. You don't need one per IC, nor do they have to be very close to IC pins; the planes themselves are the fast bypasses.

Ignore advice that recommends...

Splitting ground planes Star grounding Bypass per chip Bypass per Vcc pin Mixing cap sizes to stagger resonances Any nonsense about logic return currents

A big chip like an FPGA could have 2 to 4 ceramic caps per power rail; certainly not one per power pin.

A couple of big caps per board are good to absorb gross/slow current surges. Use aluminums or polymer tantalums, ***not*** MnO2 (conventional) tantalums.

When in doubt, use fewer caps.

John

Reply to
John Larkin

When I used to use TTL general logic (yes, that was a few years ago) I used ceramic .1 uF caps. for bypassing Vcc to ground. I was looking on the web to see if that has changed for CMOS, LVC in particular, but didn't find much. Is this still a good choice and will using an SMT cap be of much benefit to performance?

I was also looking for some simple design practice rules for CMOS, but all I found was some very long and excruciatingly detailed white papers. Is there somewhere this is netted out in a clear and concise manner?

Thanks for the help.

Dave,

Reply to
Dave Boland

I saw a largish PC board somewhere, maybe 16" square or so, that had over 3000 bypass caps.

I wonder what the world record is.

John

Reply to
John Larkin

I'm not sure of the record, but one (electrically large) design I did had well over 500 small bypass caps - I had to bypass each power pin on multiple high speed switch chips ( 192 2.5Gb/s ports on each beast, two per board) with 160 bypass devices close to the balls for each of the (multiple) power feeds. It was a fairly new device and I couldn't deviate from the mfr recommendation of one local bypass per pin. Then I had all the various ancillary stuff that took up the rest. That's not to mention the various bulk bypass that was necessary. I used adjacent power / ground planes to ease the burden as much as possible, of course.

Board size was about 12 inch by 8 inch.

I found later I could reduce the number of bypasses, but not that much, because the device had internally zoned power.

Cheers

PeteS

Reply to
PeteS

I thought I was bad. I had a ~8x12" board with 461 caps (at least C461 is the highest number in the BOM ;-). The main culprit was the Virtex-II FPGA. I followed the Xilinx APP note and flooded the backside. I only made ten of the things and time was more important than cost.

I think you found it. ;-!

--
  Keith
Reply to
Keith Williams

Thanks to all of you - the info. was very helpful!

Dave,

Reply to
Dave Boland

IFF one knows what one is doing.

If you dont have a Vcc plane, a cap per Vcc pin is not a bad idea at all. And by the time there are a few hundred of them, it would have been cheaper to use a Vcc plane....

I've done a lot of boards sans Vcc plane, and learned early on to place caps at the end of long dangly Vcc traces. The last few I did like this would have been cheaper as 6-layer PCBs, but I couldnt convince my boss of that.

Cheers Terry

Reply to
Terry Given

Fuck me! Pardon my french, but thats out of control! I've never even cracked the century. How did they find room for the ICs?

good question.

The antithesis to this is how I made a living as a tech - fixing Korean knock-off videogame PCBs. Pole Position was the worst, a couple of 2'x1' PCBs, many hundreds of LSTTL chips, 2-layer grid Vcc/0V layout, and *NO* bypass caps. A tech I knew taught me the trick of adding a bypass cap to every 5th IC (the holes were there) before looking for faults. Mysteriously, most boards were NFF after this treatment.

Cheers Terry

Reply to
Terry Given

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