on-chip bypass caps

Maybe attached to the top of the die with micro-C4s.

Cheers

Phil Hobbs

If nothing else, I'd be very syspicious of any claims with that level of accuracy. My guess is a typo.

How big is the die? How thin would the insulator have to be?

try comp.arch.fpga group ? j

I did a crude measurement of some of the balls on the FPGA, and estimated capacitances in the 10s of nF. That surprised me.

Yeah, there could be discrete caps under the lid. But 32 of them?

It doesn't look like there are caps on/in the BGA carrier, which appears to be a 12-layer PCB.

Cool, however they do it. Every chip should have internal bypasses.

My post included that group.

I vote for a typo. 501 and not 500 or 502? Or 480 or 520? They probably meant 1nF, or perhaps "5 delete" turned into "50" in front of a

Well, that would give you the least inductance, for sure.

They used to sell DIP sockets with built-in bypass caps....which unfortunately had about an inch of lead length.

Cheers

Phil Hobbs

Could you try and measure it.. power up and then discharge through a small resistor... hmm maybe measure discharge tiime w/o resistor first.

George H.

I drove some pins, balls actually, from a 50 ohm pulse generator and scoped the step response. I saw what looked like 10s of nF on some pins, but there was also clearly some ohmic loadings and active things going on that changed the apparent time constants. Not having seven hands, I couldn't connect and measure everything. But there were clearly many nanofarads.

When I designed 10 years ago the DUT power supply of an ATE family that's now testing all the processors that you're using I was given a 400nF figure. This cap was necessarily on chip since we were directly testing the wafer.

For the extreme case you can have both: embedded into the silicon plus additional under the lib.

The big processors are given for something like 100A/ns which you can't get with if you don't have that two level bypass to supplement the usual board level bulk...

The common method of marking capacitors, similar to the resistor stripe code, is two digits and an exponent of 10 in pF. Otherwise, the traditional tolerance for IC components was about 20%. (The ratio of parts on the same chip is much closer.)

Otherwise, the dielectric strength of SiO2 is about 25 MV/m (or 25V/um). At 1V you might make a capacitor at 40nm thickness. The relative dielectric constant is close (enough) to 1. Epsilon nought is about 9pf/m. C/A=epsilon nought/d=225pf/mm^2. So, about 2mm^2 would be enough.

If you could do it with a reverse biased pn junction, and I will guess that you can't, the relative dielectric constant of Si is 11.7.

Device on a chip are isolated by reversed biased pn junctions to the substrate. There should be a charge pump to get the substrate enough negative. (Remember when chips had a -5V power supply?) The capacitance, then, to the substrate through the reverse biased junction, depends on the thickness of the depletion region, which depends on the doping. Normally, you want that as low as possible, though.

-- glen

Or possibly the value from the part number, which is in pF. Two digits plus the number of zeroes to add, i.e. 501 would mean

Sounds quite likely. The original DEC Alpha CPU had about 100nF on die, and that was in the 90s. Decoupling capacitors normally use gate oxide as the dielectric, so on more modern processes the capacitance could be greater. They might not use the thinnest gate oxide for the capacitors these days as the leakage current per area starts to get quite large with very low voltage transistors.

When using place and route tools to generate logic layout from the verilog, you can set up the tools to not leave blank spaces in the layout where no gates would fit, but to put in a decoupling capacitor cell instead. Because it is embedded within the logic it helps more than a big lumped capacitor off at the edge of the logic. If necessary, you can even tell the tools to put in a certain quantity of capacitors within the logic layout even if it would have been able to pack the logic a bit more densely without.

If the package has bondwires (or comparable series inductance in the power supply pins), then these can resonate with the on-chip decoupling, to form a parallel resonant circuit that presents the chip circuitry with a very high impedance at some RF frequency. In order to avoid this effect, I used to simulate with the package model and I would break the decoupling capacitor into smaller banks and put series resistors of various values in series with some of the banks of capacitors, so that the Q is low and the impedance is reasonable at all RF frequencies of interest.

Chris

Just out of curiosity, which tools exist/do you use to go from verilog/VHDL to layout?

Pere

I never drove those tools, I was mostly doing analogue stuff. I think it is a multi-stage process, the first stage could use "design compiler" from Synopsys, and then there are various other programs involved in the physical placement and timing verification which I don't really know about. Sorry I don't know the names of them. I know these were very expensive, presumably because they could save a significant percentage of the chip area, which translates into a significant amount of money saved on production.

Chris

Well to measure the power supply cap I was thinking of powering up the chip, then turning off the power, and seeing how long it took for the voltage to decay... then repeat with a ~100(?) ohm resistor across the power line.

George H.