In altera's tool, if a .tdf file uses the parameter for that component, and if you instantiate the component in the schematic, you can change the parameter by right clicking on the symbol. I wonder if there is similar feature with VHDL file in Xilinx ISE's ECS tool. That is a convenient feature because you can instantiate as many time as you want, and just change the parameter in the schematic to customize each one of them.
Thanks, Charles
Yes. For each core you have to supply a .mpd file which defines the input and output ports of the core, and in this file you can define parameters for the core. The parameters can be assinged values be double-clicking on the core in the "Platform Studio" tool. When the cores are compiled the parameters turn into generics for VHDL code and something similar for Verilog.
-- Anders
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