SignalProbe in Quartus...

I'm trying to use SignalProbe to speed up the debugging process.

I've got a number of testpoint pins that I've been assigning and reassigning signals to in order to see the signals on an external logic analyzer.

This works very well except the 10 min. compile just to change test signals is getting old. SignalProbe seems to be the solution to my problem but I'm not able to get it going correctly.

It seems that most of the signals I want to probe are intermediate named values that connect one block of logic to another. Anyway, these signals don't appear in the signalprobe node finder.

I can type them into the assignment editor as the SignalProbe source, but the SignalProbe Compile warns that the Source "Could not be found, or is an unsupported type"

Does SignalProbe not support internal signals? Do I need to do something to make a signal a supported type?

Thanks, Ken

Reply to
Kenneth Land
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The synthesis process often removes internal nodes as the functionality is analysed and reduced to the FPGA target architecture.

If you arrange your design so that you are only trying to probe register contents (i.e. the Q's of latches etc), you can prevent the synthesis from removing these by right clicking the latch and setting the appropriate option to OFF (can't remember which one, but it's there).

If you can't find it the assignment editor, there is a parameter you can define for a synbol (megafunction or your own) to prevent register merging.

I've used signal probe quite a lot, it's pretty useful but it does use a lot of embedded memory if you try to assign plenty of nodes to it. Otherwise, you'll still need to re-compile to change which signals you're probing






Reply to
Gary Pace

Hi Ken,

To preserve a combinational node through synthesis, place and route, you should do one of the following:

a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal that you are interested in observing into a LCELL primitive, and give the LCELL primitive an interesting name, so that you can find it when you choose the Post Compilation filter in the node finder. You should feed the output of the LCELL to where the signal wof interes was previously connected.

b) If you are using VHDL or Verilog, consider using the keep pragma/keyword. Its usage is described in the online help. Search for "keep". The Verilog help panel is shown below:

------------------- keep usage in Verilog ----------------------------------- A Verilog HDL language directive that directs Analysis & Synthesis to keep a particular wire intact. You can use this language directive to keep a combinational logic node so you can observe the node during simulation or with the SignalTap® II Logic Analyzer.

You cannot use this language directive for nodes that have no fan-out.

To use the keep language directive, you can specify the keep language directive in a comment that is on the same line as the register you want Analysis & Synthesis to preserve. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis preserve */ directs Analysis & Synthesis to not minimize the keep_wire register:

wire keep_wire /* synthesis keep */;


You would search for keep_wire in the Node Finder, and you can make
assignments to it.
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Reply to
Subroto Datta

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