Hi everyone,
I am trying to design an interface between an XScale PXA255 CPU and an Altera FPGA - we have a working SRAM-like asynchronous interface, but would like to make it synchronous for improved performance and lower latency. I have been considering making the FPGA look like an SDRAM device and using the CPU's internal SDRAM controller to interface, but due to some issues with bust mode and so on, that approach could result in even higher latencies and lower throughput that the SRAM-like interface. Has anyone solved this problem before or know of a suitable way to do it? Kind regards, Hugo Vincent, Bluewater Systems