Need a few tips working with an Xilinx FPGA

I'm pretty new to FPGA-programming, and I've yet to understand quite of the steps I go through from compiling my vhdl-files, to finally generating bit-files.

I'm working with a Xilinx II Pro FPGA, using ISE 6.1i, and I'm only starting to get familiar with the tools. But I'm having some problems understanding what all the (automated) steps do, and what they actually mean.

What I want to know, is the following:

1. What does the "Translate" step do? What is actually produced by this step in the implementation ladder?
2. What happens in the "Map" stage, and what is produced?
3. What is left for "Place & Route" to do? (A whole lot I suppose, since it takes so long...)

Well, you get the picture. I'm a genuine newbie, and I want to know what the he... is going on when I skillfully double click the "Implement Design" icon :p

Any commens, or links to introductory guides will be greatly appreaciated. And I might as well warn you right away. I will probably bother you guys with questions about whe myriad of different files produced during the "implement design" process when I'm starting to undersand what is actually happening during that process.

Sincerely

-Fred, Norway.