MLC ECC with limited resources (FPGA/MCU)

Hi everyone,

Now, I'm quite new in this, so please forgive me if I say silly things.

I'm seeing whether or not it is possible (feasible) to implement MLC NAND error correction coding on our current system. We have a cortex-M3 (1MB Flash, 128K RAM) and a small FPGA with no DSP. On the FPGA I only have ~1K LUTs remaining.

After searching the internet I found that BCH most commonly mentioned as ECC scheme for MLC NAND. Also Reed-Solomon is mentioned, but it is said that RS is not suitable for MLC NAND with large page sizes (our NAND has an 8KByte page size).

What ECC scheme is best suited to be implemented on MCUs? If I would have to implement such a scheme, what functionality would you put in the MCU and what in the FPGA? Are there simpler ECC schemes which can deal with MLC NAND? Any insights are greatly appreciated!

Regards, Vincent

Reply to
Vincent vB
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Start at the beginning, and state clearly: What problem are you trying to solve?

Reply to
Dave Nadler

Hello Dave,

We put MLC NAND because we needed more storage on our PCB, but only discovered later on that our MCU's hardware ECC support is not sufficient. So, now I'm seeing whether or not we can salvage the PCBs by implementing the ECC in soft/gate-ware, or whether we need to bite the bullet and do a hardware redesign possibly using eMMC.

Regards, Vincent

Reply to
Vincent vB

Op Wed, 13 Jan 2016 16:24:59 +0100 schreef Vincent vB :

The one that best fits your application requirements.

I would put everything in the MCU, unless a significant enhancement can be had (e.g. in response time or power usage).

Why do you need a simple scheme?

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Reply to
Boudewijn Dijkstra

The issue is that I currently do not know what best meets my application requirements. I don't even know it is it feasible at all.

I did not realize until too late that the ECC scheme supported in hardware by my MCU is not good enough for the MLC NAND now on our PCB. So, I'm seeing if there is a way to salvage the already produced PCBs by using a (partial) software ECC implementation.

As far as I know most bit-wise algorithms are better suited in an FPGA. For example a BCH encoder uses Galois field polynomial division. Something which does not map very well on an MCU, as far as I understand. But maybe it does, and I did not realize. However, I do not wish to limit myself to BCH, though it does seem to be the most suitable at the moment.

I know MLC NAND Flash schemes tend to take up a lot of clock cycles and/or memory on an MCU. Maybe there is an algorithm or trade-off which uses bigger parity codes, but takes up less cycles.

Anyway, I know I am asking a rather broad and vague question. First of this is because I am not very schooled in this matter and second because I don't want to narrow the discussion in fear or missing possible solutions.

Just an elaboration of more experience people in this matter would also be helpful. Maybe others have tried to do similar things, and can share some insights.

Regards, Vincent

Reply to
Vincent vB

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