Now, I'm quite new in this, so please forgive me if I say silly things.
I'm seeing whether or not it is possible (feasible) to implement MLC NAND error correction coding on our current system. We have a cortex-M3 (1MB Flash, 128K RAM) and a small FPGA with no DSP. On the FPGA I only have ~1K LUTs remaining.
After searching the internet I found that BCH most commonly mentioned as ECC scheme for MLC NAND. Also Reed-Solomon is mentioned, but it is said that RS is not suitable for MLC NAND with large page sizes (our NAND has an 8KByte page size).
What ECC scheme is best suited to be implemented on MCUs? If I would have to implement such a scheme, what functionality would you put in the MCU and what in the FPGA? Are there simpler ECC schemes which can deal with MLC NAND? Any insights are greatly appreciated!